Pulse Width Modulation

PWM Features 特征概要 通道编程 4通道, 每通道各有一独立16位计数器, 一个通用时钟产生器,提供13种不同时钟 一个模n计数器提供11种时钟 两个独立线性分频器可对模n计数器输出再分频 通道编程 独立的使能/禁止命令 独立时钟选择 独立周期和占空比, 双缓冲系统 可编程选择输出信号极性 可编程选择输出信号是中间对齐还是左对齐 GENERAL FEATURES The PWMC controls four channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty cycle and polarity are configurable through the user interface. Each channels selects and uses one of the several clocks resulting from the division of MCK. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty cycle.

View of the external PWM’ Signals 4 路与PIOA复用的输出 专用大电流输出引脚 与 PA0，PA1 ， PA2复用 (对应 于PWM0, PWM1 和 PWM2) ，允许用户驱动外部电路的电流达到 16 mA (一般引脚为8mA) The pins used for interfacing the PWM are multiplexed with PIOA lines.

PWM into the AT91SAM7S PMC 必须首先被编程以使能PWMC的时钟 PIO 控制器需被编程以使能相应的引脚功能 置位PMC_PCER 的 bit 10 (PID10). PIO 控制器需被编程以使能相应的引脚功能 如下所示， 使用 PIO_PDR (PIO Disable Register) 禁止PIO对应的输出线 I/O Line Peripheral A Peripheral B PA0 PWM0 TIOA0 PA1 PWM1 TIOB0 PA2 PWM2 SCK0 The programmer must first enable the PWM clock in the PMC before using the PWM. 选择对应的 Peripheral A 或 B于 PIO_ASR 或 PIO_BSR， 以将PWM的各通道输出到正确的引脚.

PWM Architecture PWM 外设可被分成如下两部分 1°- PWM控制器由下列部件构成 2°- 通道模块: 时钟发生器 => 从主时钟 (MCK)产生需要的时钟 通道控制 => 使能/禁止通道 中断发生器 2°- 通道模块: 时钟选择器 通道运行方式管理器 占空比与频率控制 计数值 更新寄存器 PWM CHANNEL

PWM_MR (Mode Register) PWMC: Clock Generator PWM_MR (Mode Register) 27 24 23 16 11 8 7 PREB DIVB PREA DIVA /1 /2 /4 /8 /16 /32 /64 /128 /256 /512 /1024 1, ½,1/3,..,1/255 1, ½,1/3,..,1/255 CLKA MCK MCK is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: a modulo n counter which provides 11 clocks, MCK, MCK/2, MCK/4… Two linear dividers that provide two separate clocks: clkA and clkB. Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA & PREB fields of the PWM_MR. The resulting clock is the clock selected divided by DIVA or DIVB field value in the PWM_MR. CLKB PWM

PWMC: Channel and Interrupt Management PWM_ENA (Enable Register) PWM_DIS (Disable Register) 3 3 CHID3 CHID2 CHID1 CHID0 CHID3 CHID2 CHID1 CHID0 PWM_SR (Status Register) 3 CHID3 CHID2 CHID1 CHID0 The user can use the same control panel at interrupt level plus the dedicated mask register PWM_IER (Interrupt Enable Register) PWM_IDR (Interrupt Disable Register) PWM 3 3 CHID3 CHID2 CHID1 CHID0 CHID3 CHID2 CHID1 CHID0 PWM_IMR (Interrupt Mask Register) PWM_ISR (Interrupt Status Register) 3 3 CHID3 CHID2 CHID1 CHID0 CHID3 CHID2 CHID1 CHID0

Set up the PWMC in your Application 禁止PIO输出引脚，正确设置相关的复用引脚功能 PIO and PWM lines 处于省电考虑, PWM 的时钟在默认的情况下是关闭的 Enable the PWM Clock 设置PWM所用的时钟 Set up the Clock Generator Channel Enabling 这些任务可在设置好通道后完成 Interrupt Enabling

Set up a PWM Channel 每个通道: 通道模式寄存器: 选择通道运行模式 占空比寄存器: 16-bit 值用于选择信号的占空比 周期寄存器: 16-bit 值用于选择信号的周期 计数寄存器: 计数值 更新寄存器: 用于修改的特定寄存器, 可同时更新周期或占空比寄存器 PWM Channel 0,1,2 or 3 PWM Controller Period Control PWM pad Comparator Update Register Duty Cycle Control PWM CLKA Clock Selector CLKB CHANNEL MCK…. down to MCK/1024 Counter Interrupt

PWM_CMR (Channel Mode Register) 步骤一: 时钟选择 PWM_CMR (Channel Mode Register) 3 对通道, 通道模式寄存器允许用户从13个时钟信号中选择信号作为时钟源 CLKA CPRE CLKB /1 /2 /4 /8 /16 /32 /64 /128 /256 /512 /1024 Channel’s Counter The clock selector selects one of the clocks provided by the clock generator described just before. The internal channel counter is clocked by one of the clocks provided by the clock generator. This channel parameter is defined in the CPRE field of the PWM_CMR. CHANNEL Clock Generator

What is the best clock source ? PWM 占空比数量是第一要素: 用户必须知道其需要的最小占空比精度. 占空比控制通过一个 16-bit寄存器 PWM_CDTY 来实现. PWM_CDTY (Channel Duty Cycle Register) N value 15 CDTY 占空比数量也依赖于写入周期寄存器的值: M 值是完成一个通道周期(或中间对齐模式的半周期)所需要的事件（脉冲）数量 The large number of source clocks can make selection difficult. The relationship between the value in the Period Register and the Duty cycle register can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The higher the value of PWM_CPRD, the greater the PWM accuracy. PWM_CPRD (Channel Period Register) M value 15 CPRD PWM通道周期与M值周期相同. N 可以取自 0 到 M . M值越高, 能达到的N值也越高, 但数量就越少（周期变长）. CHANNEL

不同PWM精度的例子 第一个选择方式, 占空比精度为周期的1/75 同样的周期，这种选择方式的占空比精度可达周期的1/4800 Clock Generator CLKA Clock Generator on (/64) = Channel Period Register = 75 750 kHz 10 kHz 48 MHz CLKB 同样的周期，这种选择方式的占空比精度可达周期的1/4800 Clock Generator CLKA Clock Generator on (1) = Channel Period Register = 4800 48 MHz 10 kHz 48 MHz CLKB PWM CHANNEL

PWM_CMRx (Channel Mode Register) 如何修改一个通道的周期或者是占空比 ? 在PWM控制器中使能相应的PWM通道之前 (PWM_ENA Register): 用户可以直接写入值到相应通道的 PWM_CDTYx 或PWM_CPRDx, 即可修改通道周期与占空比 一旦PWM通道被使能: 就不能写入到前面所说的寄存器. 用户必须使用通道更新寄存器去更新前面所说的值. 更新寄存器中的值将根据PWM_CMR 中CPD 的值被写入到PWM_CDTY 或 PWM_CPRD It is possible to modulate the ouput waveform duty cycle or period. To prevent an unexpected ouput waveform when modifying the waveform parameters while the channel is still enabled, PWM_CPRD & PWM_CDTY registers are double buffered. The user can write a new period value or duty cycle value in the update register PWM_CUPD. This register holds the new value until the end of the current cycle and updates the value for the next cycle. According to the CPD field in the PWM_CMR register, PWM_CUPD either updates the PWM_CPRD or PWM_CDTY. PWM_CMRx (Channel Mode Register) 10 3 CPD CPRE PWM_CDTYx PWM_CUPDx CHANNEL 1 PWM_CUPDx

注意: 在同一PWM周期中修改同一通道的占空比与周期是不可实现的 通道更新寄存器: PWM_CUPD 为何采用: 在 运行模式, 只能通过 PWM_CUPD来更新占空比与周期, 周期或者占空比的更新将 同步 于当前计数周期的结束, 如何使用: 在写入到 PWM_CUPD之前, 用户必须确认最后一次的更新是否起效. 否则, 前一次的值将被本次修改覆盖. 使用 PWM_CMR 寄存器中的位CPD 来选择周期或占空比的修改 写入数据到 PWM_CUPD 寄存器. 注意: 在同一PWM周期中修改同一通道的占空比与周期是不可实现的 CHANNEL

PWM_CUPD 写入方式 读取PWM_ISR 自动清楚 CHIDx 标志 可采用查询或中断方式: PWM_ISR (Interrupt Status Register) 读取PWM_ISR 自动清楚 CHIDx 标志 3 CHID3 CHID2 CHID1 CHID0 PWM 可采用查询或中断方式: 标志位在周期末置位 (以通道1为例) PWM_ISR (Interrupt Status Register) 3 CHID3 CHID2 CHID1 CHID0 1 在无覆盖PWM_CUPD 值的风险的情况下可以更新通道1的周期或者占空比. CHANNEL

工作模式一: 左对齐 PWM_CMR (Channel Mode Register) CPOL PWM_CPRD PWM_CDTY 它将复位 9 8 CPOL CALG=0 Lelt-Aligned Mode PWM_CPRD PWM_CDTY CPOL= 0 CPOL= 1 CHANNEL

左对齐在多通道应用中的局限 左对齐工作方式在多通道应用中不能避免转换事件的重叠 两个通道周期 相同 PWM_CPRD0 左对齐模式下，一个事件依 赖于占空比，而另一个依赖 于周期。 由于周期相同，会有事件的 重叠 PWM_CPRD0 PWM_CDTY0 Channel 0 Output 两个通道周期 相同 (PWM_CDTY0 - PWM_CDTY1) Channel 1 Output PWM_CPRD1 CHANNEL PWM_CDTY1

工作模式二: 中间对齐 PWM_CMR (Channel Mode Register) CPOL PWM_CPRD Count down 9 8 CPOL CALG=0 Lelt-Aligned Mode PWM_CPRD Count down Count up PWM_CDTY CPOL= 0 CPOL= 1 CHANNEL

中间对齐: 无事件重叠的方法 中间对齐工作模式可避免在多通道应用中的转换事件重叠 PWM_CPRD0 PWM_CDTY0 Channel 0 Output (PWM_CDTY0 - PWM_CDTY1) Channel 1 Output PWM_CPRD1 CHANNEL PWM_CDTY1