SiFive推动RISC-V技术创新与发展 SiFive Promotes RISC-V Technology Innovation and Development SiFive推动RISC-V技术创新与发展 周杰 赛昉科技销售总监 jie.zhou@sifive.com Sept. 2019

第一代 第二代 RISC-I RISC-II What is RISC-V? A license-free, royalty-free High-quality, Suitable for all types of computing system, RISC ISA specification, Originally from UC Berkeley RISC-III (aka SOAR) RISC-IV (aka SPUR) RISC-V (Raven-1, 28nm FDSOI, 2011) RISC-I RISC-II 第一代 第二代

We invented RISC‑V Foundation David Patterson Google杰出工程师 & SiFive 技术顾问 Andrew Waterman SiFive 联合创始人 & 首席工程师 Yunsup Lee SiFive 联合创始人 & CTO Krste Asanovic SiFive 联合创始人 & 首席架构师 RISC-V历史：2010年在伯克利有一个教授和两个学生，他们需要做学生项目，当时要选一个计算机体系架构，当时选英特尔、ARM都可以选，但选这些架构来做学生项目不合适，既不能开源也不能分享。于是他们就选择自己开发。之后这个项目越做越好，从学校的环境他们崇尚开源，伯克利做的东西开源给全国，像斯坦福大学等都积极加入到这个开源项目中。到2015年的时候，业界已经有所闻，学术界也非常有名。这时候为了更好的发展这一指令集就需要有一个组织来推动这个架构，推动这个架构从技术与商业的发展。因此当时做这个项目Krste及David Patterson教授，和他们的两个学生做了两件事，一是成立一个团队（国际RISC-V基金会）来专门维护指令架构的标准化及完整性。二是建立公司SiFive来推动它的商业化。 We invented RISC‑V SiFive’s founders are the same UC Berkeley professor and PhDs who invented and have been leading the commercial implementation of the RISC‑V Instruction Set Architecture (ISA) since 2010

RISC-V发展史及其标志性事件 Privileged Arch, v1.10 RISC-V Foundation Incorporated Hot Chips 2014 1st Rocket tapeout, EOS14 45nm User ISA v2.0 IMAFD User ISA v1.0, Raven-1 tapeout (28nm) RVC MS thesis 1st Commercial Linux SoC 1st China 5 City Tour Commercial Softcores SiFive Incorporated 1st Commercial SoC Qualcomm to RISC-V NVIDIA to RISC-V 1st RISC-V Summit RedHat to RISC-V WDC to RISC-V 1st Workshop We are Here RISC-V ISA project begins First Linux Port 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

What’s Different about RISC-V? Simple Far smaller than other commercial ISAs Stable Base and standard extensions are frozen Additions via optional extensions, not new versions Clean-slate design Clear separation between user and privileged ISA Avoids µarchitecture or technology-dependent features Community designed Developed with leading industry/academic experts and software developers Modular ISA designed for extensibility/specialization Small standard base ISA, with multiple standard extensions Sparse and variable-length instruction encoding for vast opcode space

Started Development of RISC-V Core Generator Why SiFive? Leaders in RISC-V Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors Very easy to customize Silicon-proven and our licensees are shipping Raven-1 Raven-2 Raven-3 Raven-3.5 EOS14 EOS16 EOS18 EOS20 EOS22 2011 2012 2013 2014 2015 May Apr Aug Feb Jul Sep Mar Nov 2010 Started RISC-V Project 2016 2017 Oct Freedom Unleashed Base Platform Freedom Everywhere Started Development of RISC-V Core Generator Foundation SiFive team has 8 years of experience taping out RISC-V silicon....

Leaders in RISC-V Why SiFive? Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors Very easy to customize Silicon-proven and our licensees are shipping

Leaders in RISC-V Why SiFive? Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors Very easy to customize Silicon-proven and our licensees are shipping

Embedding Intelligence from the Edge to the Cloud Intelligent Edge Intelligent Cloud 64-bit Application Processors Embedding Intelligence from the Edge to the Cloud 64-bit Embedded Processors RISC-V是当今唯一种能够适用于边缘计算到云计算的处理器架构. ARM需要Cortex-M，Cortex-R, Cortex-A三种独立的Architecture Profiles, 但是残酷的现实是Cortex-M, R, A系列具有在架构上不兼容的变体。Synopsys ARC and Tensilica 处理器没有64-bit的能力. 所以为什么说RISC-V是当今仅有的一种对于智能化设备需求覆盖面最大的架构。 SiFive现今的产品家族有三大系列，分别是E，S和U系列。E系列是32位嵌入式处理器系列，S系列是64位嵌入式处理器系列，U系列是64位应用处理器系列。 【翻页】 32-bit Embedded Processors

SiFive RISC-V Core IP Product Series Production Ready Features Industry leading 32-bit and 64-bit Embedded Cores High performance 64-bit Application Cores Coherent Multi-Core Data Cache or DTIM Optional I$ and optional ITIM Singe and Double Precision FPU Optional L2 Cache Configurable Branch Prediction structures Optional User Mode Coherent, Heterogeneous Multi-Core Data Cache or DTIM Optional I$ and optional ITIM Singe and Double Precision FPU Optional L2 Cache Configurable Branch Prediction structures High Performance Embedded Optimized High-Performance Coherent Multi-Core Data Cache or DTIM Reconfigurable I$/ITIM Singe and Double Precision FPU Optional L2 Cache Configurable Branch Prediction structures Optional User Mode Coherent, Heterogeneous Multi-Core Data Cache or DTIM Reconfigurable I$/ITIM Singe and Double Precision FPU Optional L2 Cache Configurable Branch Prediction structures Small, Efficient, Performance Multi-Core RISC-V Linux Optional Harvard Pipeline CLIC with IRQ Vectoring Configurable TIMs Single Precision FPU Optional User Mode SiFive’s Most Efficient Series Features Common to all SiFive IP Products Optional RISC-V Standard Extensions: M, A, C, F, and D Configurable hardware multiplication performance Configurable number, type, and width of Ports Configurable Platform Level Interrupt Controller (PLIC) Run/Halt Debug with configurable number of breakpoints and support for JTAG and cJTAG Configurable number of Hardware Performance Counters Optional Instruction Trace Optional ECC Coherency Manager for cores configured with Data Caches SiFive Insight Architectural Clock Gating

E2 Series Features The Smallest, Most Efficient RISC-V MCU Family E2 Series core architectural overview RV32(E)IMAFDCVN capable core 2-3 stage, optional, Harvard Pipeline Efficient memory accesses Ability to add multiple outbound Ports Optional Tightly Integrated Memory (TIM) and Optional Instruction Cache First RISC-V core with support for the RISC-V Core Local Interrupt Controller (CLIC) Provides hardware interrupt prioritization and nesting Only 6 cycles to execute the first instruction of IRQ SiFive Custom Instruction Extension (SCIE) Easily add support for custom instructions

SiFive Core IP 3 and 5 series: 32-bit Embedded Processors 64-bit Embedded Processors 64-bit Application Processors Efficient Performance Coherent, Heterogenous, Multicore Hard Real-time capabilities SiFive Core IP 3 and 5 series: The world's most deployed RISC-V processor IP SiFive的3系列和5系列是SiFive最早推出的处理器产品系列，RISC-V产业中的很多“第一次”都有SiFive的3系列和5系列贡献其中，包括全世界第一个可以运行Linux的集成多核RISC-V CPU SoC芯片的开发板HiFive Unleashed是的SoC是由4核U5和单核S5组成，我们发现国内越来越多的人在全世界范围内求购这块开发板，给大家带来的好消息是SiFive已经追加了更多的产能供应市场所需。 MCU及IoT开发板HiFive1是基于E3系列，发货目的地超过全球70个国家，在今年我们推出了HiFive1的升级版本，新增了WiFi及蓝牙连接功能，对于IoT的应用开发更加有吸引力。 在会场外的SiFive站台就包含了这些展示，大家有兴趣可以去现场体验一下。 【翻页】 Configurable Efficient Mature

E3/S5 Overview High Performance 32bit and 64bit RISC-V MCUs Flexible memory architecture I-Cache can be reconfigured into I-Cache + ITIM DTIM for fast on Core Complex Data Access (D-Cache option also available) ECC/Parity Protection Off Core Complex memory access through Memory, System and Peripheral Ports Multicore Support Pre-integrated and verified by SiFive Supports up to 8+ cores Fast Interrupts Supports 16 local and up to 255 global interrupts E3/S5 with Interrupt Handlers in ITIM can enter an ISR in 10 cycles Support Vectoring for direct handler entry Does not require separate VIC Memory Protection 8 region physical memory protection Region locking E31 (AHB)* S51 (AXI)** Cortex-R5*** 28nm Area 0.066m2 0.126mm2 0.21mm2 Max Frequency 1.5GHz Typical 1.4GHz Efficiency 78 DMIPS/mW 58 DMIPS/mW 62 DMIPS/mW https://developer.arm.com/products/processors/cortex-r/cortex-r4 Min config @ 28HPM: 395MHz and 26.7µW/MHz (core only power number) 1.68/0.0267 = 62 DMIPS/mW https://sifive.atlassian.net/wiki/spaces/PROD/pages/216268828/E31+Standard+Core?preview=/216268828/323846302/E31_28hpc_200MHz_Oct2018.txt E31 200MHz worst case freq target @28nm = 200MHz E31 Typical 25C Power = 4.12mW (core only, includes leakage) E31 Efficiency = (200*1.61)/4.12mW = 70 DMIPS/mW https://sifive.atlassian.net/wiki/spaces/PROD/pages/216465469/S51+Standard+Core S51 200MHz worst case freq target @28nm = 200MHz S51 Typical 25C Power = 5.8mW (Core Only, includes leakage) S51 Efficiency = (200*1.7)/5.8mW = 58 DMIPS/mW *E31 w/ AHB Ports, PLIC w/ 127 IRQ, Debug w/ 4 hw breakpoints, CLINT, area does not include RAMs **S51 w/ AXI Ports, PLIC w/ 255 IRQ, Debug w/ 4 hw breakpoints, CLINT, area does not include RAMs ***unknown configuration: https://developer.arm.com/products/processors/cortex-r/cortex-r5

32-bit Embedded Processors 64-bit Application Processors Common Feature sets Hard Real-time capabilities Unprecedented scalability SiFive Core IP 7 series: The highest performance commercial RISC-V processor IP SiFive的7系列是2018年10月31日发布的全新产品，也是当前市场上性能最强悍的商用RISC-V处理器产品。7系列是顺序执行，双发射，8级流水线的设计，同时提升了实时性和系统扩展性的灵活性。 E7，S7以及U7同时覆盖了32位，64位嵌入式处理器以及64位应用处理器的应用。相对SiFive的5系列，CoreMarks暴增了约60%，DMIPS提升了约40%，主频提升约10%。 【翻页】 ~60% increase in CoreMarks/MHz* ~40% increase in DMIPS/MHz* 10% increase in Fmax* *Compared to SiFive 5 series

SiFive 7 series Features Scalable throughput provided by 8+1 cores per cluster Enhanced determinism for hard real-time constraints Tightly integrated memory for low latency access Functional safety provided by in-built fault tolerance mechanisms Configurable memory architecture for application specific tuning Cache lock capability for mission-critical computing 64-bit addressability for real time latency sensitive applications Extensible design via custom instructions 在此我想着重介绍一下在推出7系列的同时推出的U74-MC，支持异构多核的产品，可以由U7，S7或者E7组成多达9个RISC-V CPU core的异构多核系统。例如客户可以采用四核U74以及单核S76的配置，U74用于运行Linux，S76用于系统管理。而针对Edge端的应用，可以采用单核U74以及单核E76的配置，此时U74作为AP，E76可以作为Sensor Hub实时控制器。 相对于U74 CPU Core，S76是MicroController应用的CPU，只是去除了MMU但是增加了可选配置的TIM （tightly integrated memory)以及Fast IO接口。该Fast IO接口因为 bypass core-complex总线而达到低延时的I/O 读取。它具有一个register interface以及专属SRAM，SRAM的load-to-use的latency仅仅增加了2个cycle。 【翻页】 Mixed-precision arithmetic for efficient compute of ML workloads A single pre-integrated and verified deliverable In-cluster coherent combination of real-time and application processors

Linley MPR – “SiFive Raises RISC-V Performance”

SiFive RISC-V Standard Core Roadmap Released Std Core Denotes Early Access Standard Core Release Q4’18 Q1’19 Q2’19 Q3’19 Q4’19 Q1’20 8 Series Super Scalar 12 stage pipeline Out of Order U84 High Performance OoO AP 7 Series Dual Issue 8 stage pipeline E, S, U Cores U74 High Performance AP U74-MC Multi-Core AP U77, S77, E77 Vector Unit S76, E76 High-Performance Embedded S76-MC, E76-MC Multi-Core Embedded 5 Series Single Issue 5-6 stage pipeline Multi-Core S and U Cores U54-MC4 U54 S54 U52 No L2$ S51 3 Series Single Issue 5-6 stage pipeline Multi-Core E Cores E31 E34 2 Series Power/Area Optimized 2-3 stage pipeline E and S Cores E24 E21 E27, S27 MCU + Vector Unit E20 S21 64-bit MCU

Leaders in RISC-V Why SiFive? Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors Very easy to customize - SiFive Core Designer Silicon-proven and our licensees are shipping

SiFive is Your Virtual CPU Team Cloud-based Customize your own RISC-V core Unique for your application Not shared with your competitors SiFive Core Designer Features | Power | Performance | Area Product Specific, Unique Requirements uControllers | Embedded | Linux | Multicore Verified, Customized RISC-V IP Web Interface Verilog RTL From the Inventors of RISC-V

NEW IP PARADIGM Annual subscription allows a customer’s engineers to access SiFive’s entire processor portfolio via a simple web interface Configuring SiFive’s processor IP is fast and easy A configured processor is generated in the cloud and the results are delivered to the user’s SiFive dashboard (RTL, SDK, test bench, docs) Explore Before allows engineers to analyze their configured cores in their system simulations before committing to using them There is no processor modeling language to learn and no IP configuration tools to install FPGA bitstreams are provided to allow SW to run on a configured processor SiFive CoreDesigner RISC-V grants every user the right to modify their processor IP; SiFive has made it incredibly easy to do so.

Standard Core and Freedom Core Designer deliverables are the same. IP Deliverables Standard Core and Freedom Core Designer deliverables are the same. SiFive verifies your configuration in-house and delivers Verilog SiFive RISC-V Core IP RTL deliverable: Readable, SiFive verified, Verilog with no restrictions Delivered Configured and Integrated Bundled test bench with example tests SiFive RISC-V Core IP FPGA deliverable: Trial Variant FPGA evaluations are bitstreams of a configured core targeting our standard FPGA platforms Digilent Arty Xilinx VC707 Future FPGA platforms (Amazon F1, Microsemi Polar Fire) Trial Variant FPGA evaluations provide a useful platform for early software development and algorithm benchmarking Including a useful subsystem with peripherals like UARTs, and GPIOs

Software Development

SiFive Freedom Studio Freedom Studio Peripheral register viewer Eclipse + CDT + GNU MCU Eclipse Bundled Toolchain and OpenOCD Binaries Example software for SiFive platforms Peripheral register viewer Multicore debug support QEMU for simulation of SiFive platforms Write and validate software before having access to silicon or emulation Debug probe support OpenOCD probes such as Olimex SEGGER JLINK Supports Windows, Mac, Linux

Supported Debug Transport Hardware - JTAG Probes SiFive HiFive Unleashed & HiFive1 (FTDI) Olimex ARM-USB-TINY Probe PC (Debug Host) or Digilent Arty FPGA Debug Translator OpenOCD Debug Translator SEGGER J-Link SiFive HiFive1 revB (J-Link OB) SEGGER J-Link Probe

Leaders in RISC-V Why SiFive? Inventors of RISC-V Major contribution in most all foundation working group Leaders in RISC-V standardization Most complete product line of CPU IP: from microcontrollers, to embedded, to high-performance multi-core processors Very easy to customize - SiFive Core Designer Silicon-proven and our licensees are shipping

Our Approach Has Produced Many World’s Firsts 与微软合作实现了世界首款基于云端设计的芯片量产 世界首款基于RISC-V的SSD控制器 DDR U54 E51 OTP GbE L2$ 1.5+ GHz U54-MC SiFive CPU 1x E51: 16KB L1I$, 8KB DTIM 支持 ECC 4x U54: 32KB L1I$, 32KB L1D$ 支持 ECC 单、双精度浮点支持基于directory的2MB Banked L2$ 及cache一致性并且支持ECC ChipLink Serialized Chip-to-Chip Coherent TileLink Interconnect DDR3/4, GbE, Peripherals Freedom U540 由台积电28nm工艺制造 “SiFive基于RISC-V的IP只有其它竞品方案1/3的功耗及1/3的面积, 这能给予我们所需的灵活性以优化我们的架构来创造许多突破性的产品。” – Jihyo Lee, FADU CEO

AMAZFIT Smart Watch 2 w/ ECG RMB 999 E3 core inside AMAZFIT BIP Watch RMB 299 AMAZFIT Smart Watch 2 w/o ECG RMB 799

55 21 6/10 120 65.4M Over 50 commercial licensees worldwide 21 commercial licensees in China 6 of the top 10 semiconductor companies in the world have become SiFive customers 6/10 120 Over 100 SiFive RISC-V IP based projects in progress SiFive US completes D-round’s financing and Qualcomm becomes a new investor 65.4M

Contact Us sales@sifive-china.com marketing@sifive-china.com recruitment@sifive-china.com Best in class in RISC-V based solution with local customer support Leader in RISC-V ecosystem development to support China semiconductor industry, growing with open-source community Pioneer in cloud-based SaaS service for custom ASICs. 周 杰 赛昉科技销售总监 15381185012 jie.zhou@sifive.com