Improving the Quality of Al2O3/In0. 53Ga0

Presentation on theme: "Improving the Quality of Al2O3/In0. 53Ga0"— Presentation transcript:

1 Improving the Quality of Al2O3/In0. 53Ga0
Improving the Quality of Al2O3/In0.53Ga0.47As Interface and Ohmic contact in MOSFETs Student : Chung-Shiuan Hung, 洪崇軒 Advisor : Prof. Ming-Ham Liao, 廖洺漢教授 2014/06/23 Thanks for 昆翰, 仕宇, 思介, 崧芥, 連慶, 倡宜

2 NTU, Prof. M. H. Liao’s Group
Outline Ch. 1 Introduction Ch. 2 Investigated performance for MOSFETs with and without InP barrier layer Ch. 3 Demonstration a ultra-low contact resistivity in MOSFETs Ch. 4 Summaries 2014/6/23 NTU, Prof. M. H. Liao’s Group

3 NTU, Prof. M. H. Liao’s Group
Outline Ch. 1 Introduction Working principle of MOSFET Why III-V MOSFETs Ch. 2 Investigated performance for MOSFETs with and without InP barrier layer Ch. 3 Demonstration a ultra-low contact resistivity in MOSFETs Ch. 4 Summaries 2014/6/23 NTU, Prof. M. H. Liao’s Group

4 Working principle of MOSFET
+ + — 𝐼 𝐷,𝑠𝑎𝑡 𝑊 𝑔 ∝ κ ε 0 𝜇 𝑒𝑓𝑓 𝑡𝑜𝑥 𝐿 𝑔 𝑉 𝐺 − 𝑉 𝑡ℎ 2 8.85…×10⁻¹² F/m source中興物理 孫允武 2014/6/23 NTU, Prof. M. H. Liao’s Group 4

5 NTU, Prof. M. H. Liao’s Group
Why III-V MOSFETs Manufacturing Development Research 130nm 90nm 65nm 45nm 32nm 22nm 15nm ??? Source: Intel Cu/low-k High-k metal gates n: III-V 70年代早期: Lg~20um Tox~1000A Vd=12V 因為納汙染的緣故 大多使用PMOSFET 70年代中期: Lg~15um Tox~300A Vd=12V 採用離子佈值 80年代 : Lg~2um Tox~400A Vd=5V CMOS 1985 1989 Spacer LDD metal-gates 基本物理限制是什麼限制?? Source: Strained Si p: Ge 𝐼 𝐷,𝑠𝑎𝑡 𝑊 𝑔 ∝ κ ε 0 𝜇 𝑒𝑓𝑓 𝑡𝑜𝑥 𝐿 𝑔 𝑉 𝐺 − 𝑉 𝑡ℎ 2 2014/6/23 NTU, Prof. M. H. Liao’s Group

6 Why III-V MOSFETs Advantages of the III-V
III-V semiconductor is a possible solution (for nMOS) due to the high electron μ and light electron m*eff. Advantages of the III-V High electron mobility sophisticated band-gap engineering improved power/performance tradeoff IV III-V Material Si Ge GaAs In0.53Ga0.47As InAs InSb Electron Mobility (cm2/Vs) 1,400 3,900 8,500 12,000 40,000 77,000 Hole Mobility (cm2/Vs) 450 1,900 400 500 850 Band gap(eV) 0.11 0.67 1.42 0.74 0.36 0.17 2014/6/23 NTU, Prof. M. H. Liao’s Group

7 NTU, Prof. M. H. Liao’s Group
Outline Ch. 1 Introduction Ch. 2 Investigated performance for MOSFETs with and without InP barrier layer MOS diode and MOSFET fabrication MOS diode and MOSFET Characteristics Conclusions Ch. 3 Demonstration a ultra-low contact resistivity in MOSFETs Ch. 4 Summaries 2014/6/23 NTU, Prof. M. H. Liao’s Group

8 Backside metal contact
MOS diode fabrication ALD-Al2O3 Shadow mask Shadow mask Metal-Gate In0.53Ga0.47As InAlAs Buffer InP substrate Backside metal contact 2014/6/23 NTU, Prof. M. H. Liao’s Group

9 MOS diode Characteristics
Without InP With InP 論文中採用高頻-低頻法，為目前最常用來計算Dit的方法之一，此方法是比較高頻和低頻之電容對電壓曲線的差異，進而推算出Dit的大小，其原理為界面缺陷電42 荷(Interface trap charge, Qit)會隨著閘極偏壓的變化而捕抓及釋放電荷。對高頻量測而言，界面缺陷進行捕捉電荷的速度跟不上頻率的變化，但會受到閘極直流訊號的影響，當外加偏壓從累積區到反轉區(inversion region)改變時，介面缺陷電荷會隨著偏壓而發生微小的變化，造成半導體表面位能的改變，因此高頻曲線會隨著電壓變化而有延展(stretch-out)的現象。對低頻量測而言，低的頻率可讓界面缺陷跟上交流訊號反應而貢獻電容，噵致曲線有扭曲現象。因此，透過缺陷受到高低頻率的影響而得到電容電壓曲線，便可從曲線變化來計算Dit，下列即為Dit的計算公式： (3-7)       ox C hf C ox C hf C ox C if C ox C if C qA C D ox it / 1 / / 1 / 其中Cif 為低頻量測之電容值，Chf 為高頻量測之電容值，Cox 為累積區之電容值，A 為電容器面積。使用此方法的優點為不需計算理想的半導體電容值，可經由實驗量測所得到的高低頻電容數據，直接換算出Dit，然而缺點為低頻的曲線可能因漏電流大為提升的狀況下而難以量測。 Dit (1/cm2eV) by high low method 　Al2O3/In0.53Ga0.47As ≈2.76E12 (-1V~0V) 　Al2O3/InP/In0.53Ga0.47As ≈1.22E12 (-0.5V~0.5V) 2014/6/23 NTU, Prof. M. H. Liao’s Group

10 NTU, Prof. M. H. Liao’s Group
MOSFET fabrication Sputter-TiN 150nm + ALD - TiN 15nm ALD-Al2O3 (5nm) In0.53Ga0.47As In0.53Ga0.47As(100nm) (100nm) InP (4nm) In0.53Ga0.47As　　　　　　 (10nm) InAlAs Buffer　　　　 (300nm) RTA 400℃ 5min InP substrate 2014/6/23 NTU, Prof. M. H. Liao’s Group

11 NTU, Prof. M. H. Liao’s Group
MOSFET fabrication (Source) (Drain) (Gate) Contact metal In0.53Ga0.47As(100nm) (100nm) Al2O3 InP (4nm) In0.53Ga0.47As　　　　　　 (10nm) InAlAs Buffer　　　　 (300nm) InP substrate 2014/6/23 NTU, Prof. M. H. Liao’s Group

12 MOSFET Characteristics
Surface Channel Buried Channel Enhance 20% 2014/6/23 NTU, Prof. M. H. Liao’s Group

13 NTU, Prof. M. H. Liao’s Group
Conclusions Insert InP into Al2O3 and InGaAs reduce density of interface states of high-K/InGaAs →Enhance drain current ( 142 → 175 mA/mm; 20% ) →Enhance transconductance ( 110 → 140 mS/mm; 21% ) → Reduction of the subthreshold slope( 196 → 113 mV/dec) W/O InP With InP Id,max 142 mA/mm 175 mA/mm Gm 110 mS/mm 140mS/mm Ioff 0.06 mA/mm 0.009 mA/mm SS 196 mV/dec 113 mV/dec 2014/6/23 NTU, Prof. M. H. Liao’s Group

14 NTU, Prof. M. H. Liao’s Group
Outline Ch. 1 Introduction Ch. 2 Investigated performance for MOSFETs with and without InP barrier layer Ch. 3 Demonstration a ultra-low contact resistivity in MOSFETs Transmission line method(TLM) Source/Drain contact metal Conclusions Ch. 4 Summaries 2014/6/23 NTU, Prof. M. H. Liao’s Group

15 Transmission line method
H. H. Berger, “Model for Contacts to Planar Devices,” Solid-State Electron., 15, 145 (1972). “Transmission line method” (TLM) is used to extract the Rc and ρc. The patterns of TLM is shown in left-side and the relationship is given by and 𝑅 𝑇 = 𝑅 𝑠𝑑 𝑑 𝑍 +2 𝑅 𝑐 ≈ 𝑅 𝑠ℎ 𝑍 𝑑+2 𝐿 𝑇 此方法最先由Helmuth Murrmann and Dietrich Widmann提出 後來經IBM Lab H. H. Berger提出一個簡化的模型, 始之能更方便萃取出 pc。 𝜌 𝑐 = 𝑅 𝑠ℎ ∙ 𝐿 𝑇 2 2014/6/23 NTU, Prof. M. H. Liao’s Group

16 Ni Ohmic contact on n-InGaAs
Annealing Temp. 10s 30s 60s 5min As deposited 1.8×10-6 150℃ 4.1×10-6 5.4×10-6 7.5×10-6 9.4×10-6 200℃ 5.3×10-6 5.5×10-6 5.1×10-6 7.7×10-6 250℃ 6.0×10-6 7.1×10-6 2.2×10-6 300℃ 9.2×10-6 8.5×10-6 1.2×10-5 2.8×10-5 400℃ 3.3×10-5 2.4×10-5 4.2×10-6 (W-cm2) (W-cm2) 2014/6/23 NTU, Prof. M. H. Liao’s Group

17 Pd/Ge/Ti/Au Ohmic contact on n-InGaAs
Annealing Temp. 10s 30s 60s 5min As deposited 1×10-7 200℃ 2.4×10-7 1.5×10-7 1.9×10-7 3.5×10-7 300℃ 3.4×10-7 1.7×10-6 8.4×10-6 9.7×10-6 400℃ 1.8×10-6 4.6×10-6 6.4×10-6 (W-cm2) 2014/6/23 NTU, Prof. M. H. Liao’s Group

18 Ge/Ni Ohmic contact on n-InGaAs
Annealing Temp. 10s 30s 60s 3min 5min 7min 200℃ 7.7×10-7 6.6×10-7 5.8×10-7 7.3×10-7 300℃ 8.8×10-7 1.1×10-6 1.7×10-6 2.7×10-6 400℃ 2.3×10-6 2×10-6 1.2×10-6 9.1×10-7 (W-cm2) 2014/6/23 NTU, Prof. M. H. Liao’s Group

19 Device Characteristics- In0.53Ga0.47As MOSFETs
Pd/Ge/Ti/Au Ni contact Enhance 31% 19 2014/6/23 NTU, Prof. M. H. Liao’s Group

20 NTU, Prof. M. H. Liao’s Group
Conclusions Reduce S/D contact resistance rC : 1.8E-6 → 4.6E-7 W-cm2 →Enhance drain current( 175 → 253 mA/mm; 31%) →Enhance transconductance( 140 → 172 mS/mm; 19%) S/D contact metal Ni Pd/Ge/Ti/Au Id,max 175 mA/mm 253mA/mm Gm 140 mS/mm 172mS/mm Ioff 0.009 mA/mm 0.014mA/mm SS 113 mV/dec 121mV/dec 2014/6/23 NTU, Prof. M. H. Liao’s Group

21 NTU, Prof. M. H. Liao’s Group
Outline Ch. 1 Introduction Ch. 2 Investigated performance for MOSFETs with and without InP barrier layer Ch. 3 Demonstration a ultra-low contact resistivity in MOSFETs Ch. 4 Summaries 2014/6/23 NTU, Prof. M. H. Liao’s Group

22 NTU, Prof. M. H. Liao’s Group
Summaries MOSFET (a)Implant free S/D (b)High S/D doping concentration (c)Low thermal budget Insert InP (a)QW-MOSFET (b)Improved the interface quality Ohmic contact (a)Reduce S/D contact resistance →Enhance drain current Id=142 mA/mm Gm=110 mS/mm SS=196 mV/dec Id=175 mA/mm Gm=140mS/mm SS=113 mV/dec Id=253mA/mm Gm=172mS/mm SS=121mV/dec 2014/6/23 NTU, Prof. M. H. Liao’s Group

23 NTU, Prof. M. H. Liao’s Group
2014/6/23 NTU, Prof. M. H. Liao’s Group