Introduction to PG & LA Digital Circuit Lab TA: Po-Chen Wu.

Presentation on theme: "Introduction to PG & LA Digital Circuit Lab TA: Po-Chen Wu."— Presentation transcript:

1 Introduction to PG & LA Digital Circuit Lab TA: Po-Chen Wu

2 Outline Programmable Data Generator Logic Analyzer
Complete the RSA System

3 Programmable Data Generator

4 Introduction to PG Programmable data generator (PG in brief) is powerful of generating several kinds of digital waveforms. Combining logic analyzer (LA) and PG will make an auto testing system or auto verification system.

5 System Properties Setup
1 每次打開PG程式時都要確保是3.3V 2 (for GPIO) 3

6 Wave Editor 1

7 Definitions Label (signal name) Channel (POD order from left to right)
Labels can be defined as numeric, alphabetic, underscore _, [, or], yet their length cannot be over 31 characteristics (bytes). Channel (POD order from left to right) Pod A = CH-00 ~ CH-09 Pod B = CH-10 ~ CH-19 Extended Pod = Event_1, …, Clock_Out Well, just take them as 0~9

8 Zoom in & Zoom out Note! The base point is the Address Stamp of the waveform field whenever the waveform is either zoomed in or zoomed out. zoom out & zoom in Address stamp

9 Set Parameter 1

10 PG is positive-edge-triggered.
1 (internal clock frequency) 2 (keyboard event) 3 (cursor change time gap, the cursor transformation depends on it) 4 Cursor Drag mode When you stop the Drag cursor for a while, it will restore to Point cursor. Point mode You just move Point cursor quickly then the Point Cursor will change to be Drag cursor automatically.

11 Add Label 1 2 3 4 5

12 1 3 2 4 5 6

13 3 1 press & drag 2

14 3 1 4 2 5 6 7 press & drag 10對應到addr[4], 6對應到addr[0]
以此類推, 18~11對應到data_i[7:0] 5 6 14 7

15

16 Command Setting There is one label named PG_Function in waveform field cannot be deleted. You may set PG_Function command to control the waveform output flow. Name Intruction Description NP No Operation No action SE Set Event Set Event to be a trigger WE Wait Event Stop for waiting Event received …

17 2 1 3 4 (the ready signal) 現在的Event是當Event 1為1時，也就是當ready為1時 5 16

18 2 1 3 4

19

20 request for a0 Finished!! …?

21 Before Running After finished waveform check and reported no errors, you may click Run button to output these data. PC will take 0.5~1 second to transform these data into PG through USB port. The tip of running PG is to insert Set Keyboard Event and Wait Event command in the empty front area of waveform field.

22 2 1 3 4 5

23 2 1 3 4

24 Finished!!!

25 Save PG File 1 2 3 4

26 Load PG File 1 2 3

27 Double click ⇒ Doesn't work!
(It only open the PG software but does not load the waveform file. So you have to load it again.)

28 Logic Analyzer

29 Introduction to LA Logic Analyzer (LA in brief) is used to observe the output signals from other devices. TravelLogic series (which are used in our experiments) has 36 channels.

30 1 2

31 1

32

33 1 3 5,6 4 2 7

34

35 Trigger Position

36 1 2

37 The sampling rate ideally should be 5-10 times of the frequency of the target signal.

38 1 2

39

40 Save LA File 1 3 2 4

41 Load LA File 1 2 (double click) 3

42 Complete the RSA System

43 System Overview DE2-115 PG LA clk reset ready we oe start reg_sel addr
data_i clk _o reset _o ready _o we _o oe _o start _o reg_sel_o addr_o data_i _o data_o LA 如果compile時出現以下的error message: Cell <name> fed by <number> non-global control signals -- only <number> control signals may be non-global (ID: ) clk和reset在GPIO的位置需要挑過，並不是所有的pin腳都可以被assign此二值 以下的pin腳assignment是測試過且可work的，供大家參考: clk: AF26 reset: AD21

44 Connect PG Components (1/3)

45 Connect PG Components (2/3)

46 Connect PG Components (3/3)

47 Connect LA Components (1/2)

48 Connect LA Components (2/2)

49 1

50 1 2 Push Space Key

51 擷取資料之後，下方的捲軸就不能拉動了 只能透過鍵盤的左右鍵改變trigger position的位置，進而觀測不同位置的訊號 在變數的位置按滑鼠右鍵→設定訊號參數 可將數值型態改成是ASC(ASCII)，即可看到文字訊息

52 How to Optimize? (1/2) Modify the constraint file exp2_rsa.sdc and then compile again. Ex: Change the signal frequency of PG and check if the result is still correct. Don’t forget to change the sampling rate of LA. Record the min. clock period (max freq.). create_clock -period 500 [get_ports clk] derive_clock_uncertainty set_input_delay 0 -clock clk [all_inputs] set_output_delay 0 -clock clk [all_outputs] .sdc的clock period是我們希望電路能達到的目標值 設的越低，理論上合出來的電路會跑得越快，但相對的面積也可能越大 不過目標值和實際值之間一定會存在著落差 所以還是要實際用PG測量才能確定電路的最快時脈為多少 另外period設太低，是有可能將compile時間拉得非常長的 如果我們設period為1這種天方夜譚的數字 Quartus II可能會compile很久也合不出來 (但也有可能它一看這數字太扯，便直接合一個它認為最快的電路交差了事)

53 How to Optimize? (2/2) Modify the testbench
clock period to min. clock period TEST_DATA to 6 Run the Verilog simulation to get the finish time.

54 The End. Any question?

55 Reference "DE2-115 User Manual" by Terasic Technologies Inc.
"enPG.pdf" by Acute Technology Inc. "enLA.pdf" by Acute Technology Inc.