RAIL-to-RAIL OP AMPS 轨至轨运放的设计

Presentation on theme: "RAIL-to-RAIL OP AMPS 轨至轨运放的设计"— Presentation transcript:

1 RAIL-to-RAIL OP AMPS 轨至轨运放的设计

2 主要内容 设计原理 采用电平移位法轨至轨运放的设计 采用恒定电压法实现跨导恒定的设计

3 Op Amp Configurations

4 Why Rail-to-Rail Differential Input Stage?

5 问题 为什么要提高运放的输入信号共模范围？ 为什么要实现跨导的恒定？

6 How to Obtain a Rail-to-Rail Input Common Mode Range?
(a) P-type differential input stage (b) N-type differential input stage

7 How to Obtain a Rail-to-Rail Input Common Mode Range?

8 How to Obtain a Rail-to-Rail Input Common Mode Range?

9 combining a PMOS and a NMOS Differential pairs

10 combining a PMOS and a NMOS Differential pairs

11 Why is a Constant Gm needed ?

12 Techniques for N-P Complementary Rail-to-Rail Input Stage
1. For input stages with input transistors working in weak-inversion region, using current complementary circuit to keep the sum of IN and IP constant [1][2][6]; 2. Using square root circuit to keep constant [3][13][16]; 3. and 4. Using current switches to change the tail current of input differential pairs [3][4][5][6]; 4. Using hex-pair structure to control the tail currents of backup pairs [7];

13 Techniques for N-P Complementary Rail-to-Rail Input Stage( cont’d )
5. Using maximum/minimum selection circuit to conduct the output current of the differential pair with larger current, as well as larger gm,to the next stage [8][9]; 6. Using electronic zener diode to keep constant [10]; 7. Using DC level shift circuit to change the input DC level [11]. We will analyze them one by one in the following sections. There are still other techniques [12][14][15][17][18], interested readers may check these references.

14 Rail-to-Rail Input Stage, Structure 2
Basic idea – For an input differential pair, using a 1st order approximation,

15 Rail-to-Rail Input Stage, Structure 3 [3][4][6]
Using current switches to change the tail current of input differential pairs

16 具体电路

17 Rail-to-Rail Input Stage, Structure 6 [8][9]
Using Maximum/Minimum selection circuit

18 The block diagram

19 最大电流选择电路

20 Rail-to-Rail Input Stage, Structure 7
Using DC shifting circuit to change the input DC level

21 具体电路

22 Rail-to-rail amplifier with Zener diode

23 Summary and Comparison

24 进一步研究的问题 Mismatch between N-channel and P-channel transconductors
Transition Region CMRR degradation (40-60 dB) Nonlinearity

25 References I [1] J. F. Duque-Carrillo, J. M. Carillo, J. L. Ausin, and E. Sanchez-Sinencio, “Robust and universal constant-gm circuit technique,” Electronics Letters, vol. 38, no. 9, pp , Apr [2] M. Wang, T.L. Mayhugh, S.H.K. Embabi, and E. Sanchez-Sinencio, “Constant-gm Rail-to-Rail CMOS Op-Amp Input Stage with Overlapped Transition Regions,” IEEE J.of Solid State Circuits, vol. 34, no. 2, pp , Feb [3] G. Ferri and W. Sansen, “A Rail-to-Rail Constant-gm Low-Voltage CMOS Operational Transconductance Amplifier,” IEEE J. of Solid State Circuits, vol. 32, no.10, pp , Oct [4] J. Ramirez-Angulo, R.G. Carvajal, J. Tombs, and A. Torralba, “Low-Voltage CMOS Op-Amp with Rail-toRail Input and Output Signal Swing for Continuous-Time Signal Processing Using Multiple-Input Floating-Gate Transistors,” IEEE Trans. On Circuits and Systems – II, vol. 48, no. 1, pp , Jan 2001. [5] J.M. Carrillo, J.F. Duque-Carrillo, G. Torelli, and J.L. Ausin, “General Purpose rail-to-rail input circuit with constant behavior for VLSI cell libraries,” IEEE International Symposium on Circuits and Systems, vol. 3, pp , May 2002

26 References II [1] J. H. Huijsing, and D. Linebarger, “Low voltage operational amplifier with rail-to-rail input and output stages,” IEEE Journal of Solid-State Circuits, vol. SC-20, no.6, pp , December 1985 [2] W.-C. S. Wu, W. J. Helms, J. A. Kuhn, and B. E. Byrkett, “Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges,”IEEE Journal of Solid-State Circuits, vol. 29 , no. 1, pp , January 1994 [3] R. Hogervorst, R. J. Wiegerink, P. A. L. de Jong, J. Fonderie, R. F. Wassenaar, and J. H. Huijsing, “CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage,” IEEE Proc. ISCAS 1992, pp [4] R. Hogervost, J. P. Tero, R. G. H. Eschauzier and J. H. Huijsing, “A compact power-efficient 3-V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries,” IEEE Journal of Solid-State Circuits, vol. 29, no. 12, pp , December 1994 [5] R. Hogervorst, S. M. Safai, and J. H. Huijsing, “A programmable 3-V CMOS railto-rail opamp with gain boosting for driving heavy loads,” IEEE Proc. ISCAS 1995, pp [6] J. H. Huijsing, R. Hogervorst, and K.-J. de Langen, “Low-power low-voltageVLSI operational amplifier cells,” IEEE Trans. Circuits and Systems-I, vol. 42. no.11, pp , November 1995

27 References ( cont’d ) [7] W. Redman-White, “A high bandwidth constant gm, and slew-rate rail-to-rail CMOS input circuit and its application to analog cell for low voltage VLSI systems,” IEEE Journal of Solid-State Circuits, vol. 32, no. 5, pp , May 1997 [8] C. Hwang, A. Motamed, and M. Ismail, “LV opamp with programmable rail-to-rail constant-gm,” IEEE Proc. ISCAS 1997, pp [9] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm input-stage architecture for low-voltage op amps,” IEEE Trans. Circuits and Systems-I, vol.42. no. 11, pp , November 1995 [10] R. Hogervost, J. P. Tero, and J. H. Huijsing, “Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode,” IEEE Journal of Solid-State Circuits, vol. 31, no. 7, pp , July 1996 [11] M. Wang, T. L. Mayhugh, Jr., S. H. K. Embabi, and E. Sánchez-Sinencio,“Constant-gm rail-to-rail CMOS op-amp input stage with overlapped transition region,” IEEE Journal of Solid-State Circuits, vol. 34, no. 2, pp ,February 1999 [12] G. Ferri and W. Sansen, “A rail-to-rail constant-gm low-voltage CMOSoperational transconductance amplifier,” IEEE Journal of Solid-State Circuits, vol.32, no. 10, pp , October 1999

28 References ( cont’d ) [13] S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage,” IEEE Journal of Solid-State Circuits,vol. 31, no. 2, pp , February 1996 [14] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “Simple rail-to-rail lowvoltage constant transconductance CMOS input stage in weak inversion,” Electronics Letters, vol. 29, no. 12, pp , June 1993 [15] V. I. Prodanov and M. M. Green, “Simple rail-to-rail constant transconductance input stage operating in strong inversion,” IEEE 39th Midwest Symposium on Circuits and Systems, vol 2, pp , August 1996 [16] J. H. Botma, R. F. Wassenaar, and R. J. Wiegerink, “A low voltage CMOS op amp with a rail-to-rail constant-gm input stage and a class AB rail-to-rail output stage,”IEEE Proc. ISCAS 1993, vol. 2, pp , May 1993 [17] J. F. Duque-Carrillo, J. M. Valverde, and R. Perez-Aloe, “Constant-gm rail-to-railcommon-mode range input stage with minimum CMRR degradation,” IEEE Journal of Solid-State Circuits, vol. 28, no. 6, pp , June 1993 [18] A. L. Coban and P. E. Allen, “A low-voltage CMOS op amp with rail-to-rail constant-gm input stage and high-gain output stage,” IEEE Proc. ISCAS 1995, vol.2, pp , April-May 1995

29 References ( cont’d ) [19] T. W. Fischer, A.I. Karsilayan, and E. Sánchez-Sinencio, “A Rail-to-Rail Amplifier Input Stage with +/-0.35% gm Fluctuation,” IEEE Transactions On Circuits and Systems I. vol. 52, No. 2, pp , February 2005. [20] J. Hu, S. Yan, and E. Sánchez-Sinencio, “A Constant-GM Rail-to-Rail Op Amp Input Stage Using Dynamic Current Scaling Techniques,” IEEE International Symposium on Circuits and Systems, Kobe, Japan, May 23-26, 2005. [21] S. Yan, J. Hu, T. Song, and E. Sánchez-Sinencio, “Constant-gm Techniques for Rail-to-Rail CMOS Input Stages: A Comparative Study,” IEEE International Symposium on Circuits and Systems 2005, Kobe, Japan, May 23-26, 2005. [22] T. Song, J. Hu, X. Li, S. Yan and E. Sánchez-Sinencio, " A Robust and ScalableConstant gm Rail-to-Rail CMOS Input Stage with Dynamic Feedback for VLSI Cell Libraries", IEEE Transactions on Circuits and Systems I, pp , Vol. 55, Issue 3, April 2008.

30 一种采用电平移位法的恒跨导轨至轨运放的设计

31 设计指标 参数名 设计值 电源电压（VDD） 3.3v 开环增益（RL=10k，CL=10pf） >80dB
60度 单位增益带宽（RL=10k，CL=10pf） >5MHz 转换速度 （CL=10pf） >10v/us 共模抑制比 电源抑制比 输入共模范围 0-3.3v 输出摆幅 跨导变化率 <5%

32 轨至轨特点 一、输入输出信号范围尽可能大，从Vss到Vdd。 二、输入级的跨导在共模输入电压范围内基本保持恒定。

33 互补差分输入级 1、低共模输入：PMOS饱和，NMOS截止 2、高共模输入：NMOS饱和，PMOS截止
3、输入级最小电源电压：Vsup=Vsgp+Vgsn+2Vdsat 4、共模输入范围为VSS≤Vcm≤VDD

34 PMOS/NMOS互补差分对的致命缺陷：在整个共模输入范围内，输入电路的总跨导不恒定。

35 电平移位法恒定跨导 一、原理 平移PMOS对或者NMOS对的跨导曲线，使中间重合的部分正好为恒定的常数，且同非重合部分相等。

36 1、首先要求非重叠部分 即需满足： 和 2、确定平移的量 也就是讨论NMOS（或PMOS）对的跨导的2个转折点。

37 二、平移电路 采用输入端接入共源电路的方法。利用MOS管的栅源电压来抬高或降低输入共模电压的范围从而达到平移跨导曲线的目的。这里采用的是PMOS对的左平移法。 利用Mb2，Mb3，M5，M6构成共源电路来对PMOS差分对的跨导 进行平移， 平移的大小为

38 三、半定量分析 1、NMOS管M3开始工作， ，得出 2、Vcm增大，直到M3，M4，Mbn都进入饱和区，得出
同理，可以求出PMOS对的2个转折点，如下： 3、Vcm从Vdd减小到M1开始导通得出 4、Vcm再减小时，M1，M2，Mbp进入饱和状态，得出

39 根据电平位移法的原理，得出以下方程式： 简化后，两式相减可得出： 分解为 即

40 所以满足： 和 这两个条件。 可知 M1和M3的宽长比之比。 由 可算出 由 得 由 可得出Mb2的宽长比。

41 ClassAB输出级结构 mos管工作在饱和区时 令 则 满足输出跨导恒定

42 Rail to Rail电路的实际宽长比的手工计算
一、输入级参数计算 从CSMC 0.5um MIX工艺库文件中得到工艺参数 设

43 Rail to Rail 输入级实际电路图

44 按照平移法原理的分析 取 则 设平移电路的电流 再计算

45 二、输出级参数计算 再综合考虑为保证M30-M31能工作在饱和区，设 则 G30由前级决定为常数， 确定 这里设2.25v。 得出
实际的rail-to-rail输出级电路图 再综合考虑为保证M30-M31能工作在饱和区，设 得出

46 三、中间级共源共栅参数计算 总增益 中间级共源共栅电路图

47 根据设计指标和电路原理手工计算得出的MOS宽长比

48 Rail_To_Rail放大器 ——采用恒定电压法实现跨导恒定的设计

49 结构与原理 当共模信号Vicm很大时，此时只有NMOS差分对(M13,M14)导通，PMOS差分对(M11,M12)截止，此时的跨导大小为：
当共模信号Vicm很小时，此时只有PMOS差分对（M11,M12）导通，NMOS差分对（M13,M14）截止，此时的跨导大小为：

50 结构与原理 当共模信号Vicm处于中间时，此时NMOS、PMOS差分对均会导通，此时的跨导大小为： 每个管子通过的电流为4Iref
注：这里所有的推导是假设 每个管子通过的电流为4Iref 中间跨导是两边跨导的一倍

51 随着共模信号的增大互补差分对的工作情况

52 解决方案 保持跨导恒定的方法 降低中间跨导 1）减少共模信号处于中间状态时电流
2）怎样控制电流使得在 处于较大以及较小的情况下分别保持NMOS、PMOS差分对中的电流保持不变4Iref 增加并联二极管支路

53 定量的计算 解之得 处于中间状态时,流过NMOS、PMOS差分对中的电流为Iref而不是4Iref 二极管支路的电流为多少？

54 二极管支路 采用稳压管 显然这是很难做到的。 当 处于较大时，由于NMOS差分对导通，则 ， PMOS差分对不导通，则
一是，稳压管的制作工艺与标准的CMOS工艺是不兼容的。 二是，在稳压管正常工作的情况之下，如何精确的控制流过其中的电流为6 显然这是很难做到的。 当 处于较大时，由于NMOS差分对导通，则 ， PMOS差分对不导通，则 从而稳压电路Ｚ是不导通的。 当 处于较小时，与上面的分析同理。

55 处于中间状态的情况 此时PMOS，NMOS差分对均处于导通状态，如果没有稳压管的情况下， 显然 这时稳压管正常的导通。

56 处于中间状态时，流过二极管支路的电流是6Iref
其中 由上面的假设 ,则 同理可知， M11的栅极G11与M16的栅极G16是等位点

57 管子的尺寸

58 电阻与电容

59 存在的误差 共模电压处于较大以及较小的情况支路有小电流 MOS管导通与截止存在缓慢变化过程 伏安特性非理想 P管与N管非对称 如何消除？