Download presentation
Presentation is loading. Please wait.
1
授課教授 : 陳永耀 博士 學生 : 藍浩濤 P90921001 電機所控制組
全新架構的全數位式無類比鎖相倍頻電路 Create DLL circuit and Multiple frequency with VHDL or VERILOG in CPLD,FPGA or ASIC 授課教授 : 陳永耀 博士 學生 : 藍浩濤 P 電機所控制組
2
OUTLINE Conclusions Abstract Purposes of DLL
DLL Definition and Principle Circuit Design with VHDL in CPLD and FPGA Flowchart Simulation Wave for Lattice CPLD Experimental Results on Oscilloscope Conclusions
3
Abstract DLL usually implements with logic and analog circuit in ASIC design. CPLD and FPGA are logic devices,and must design DLL or PLL to implement in devices design first. Could we create a simple DLL circuit with VHDL or Verilog implementing in CPLD, FPGA or ASIC ?
4
Purposes of DLL ADC and DAC CPU design Single chip design SOC design
DDR design Wireless circuit DSP
5
DLL definition and principle
DLL ( Delay Lock Loop )
6
Circuit design with VHDL in CPLD and FPGA Flowchart
Language Description RTL ( Register Transfer Level) Transfer to RTL format Cell Mapping Optimal circuit Auto Compiler Flow in CPLD and FPGA Netlist of circuit
7
Simulation Waves for Lattice CPLD
Lattice 2032VE-110 Lattice 2064VE-100 Lattice M4A3-256/100 Altera EPM7032LC44-6
8
Lattice 2032VE-110
9
Lattice 2032VE-110
10
Lattice 2064VE-100
11
Lattice M4A3-256/100
12
Altera EPM7032LC44-6
14
Experimental Results on Oscilloscope
Lattice M4A3-256/160-10YC 及電路板實際外觀
15
Lattice 2064VE-100LT100 及電路板實際外觀
16
Lattice M4A3-256/160-10YC 延遲的輸出波形
17
Lattice M4A3-256/160-10YC 倍頻的輸出波形
18
Lattice 2064VE-100LT100 鎖相的輸出波形
19
Lattice 2064VE-100LT100 鎖相的輸出波形
20
Lattice 2064VE-100LT100 延遲的輸出波形
21
Lattice 2064VE-100LT100 鎖相的輸出波形
22
Lattice 2064VE-100LT100 鎖相的輸出波形
23
Lattice 2064VE-100LT100 倍頻的輸出波形
24
儀器誤差+電路板誤差+測試棒誤差+測試棒接點電阻延遲誤差+電路板RC延遲誤差 = 900ps
Lattice 2064VE-100LT100 延遲的輸出波形 儀器誤差+電路板誤差+測試棒誤差+測試棒接點電阻延遲誤差+電路板RC延遲誤差 = 900ps
25
Conclusions 鎖相只需一個 延遲時間(only one locking time) 只有靜態耗電，沒有動態耗電
可輕易的實現於CPLD，FPGA，ASIC Fully IP 無Jitter 完全沒有類比電路，也不需要IC外部的電阻電容或者是電感 無VCO 內部震盪器
Similar presentations
