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第13章 时序电路分析 2018/12/5 逻辑设计基础
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13.1 时序奇偶校验器 2018/12/5 逻辑设计基础
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Fig. 13-1: Block Diagram for Parity Checker
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Figure 13-2: Waveforms for Parity Checker
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Figure 13-3: State Graph for Parity Checker
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Table 13-1: State Table for Parity Checker
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Figure 13-4: Parity Checker
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13.2 信号跟踪及时序图分析 由输入序列导出输出序列步骤: 假设触发器的初态(一般清零)。
对于给定输入序列的第一个输入,确定电路的输出和触发器输入。 确定下一个有效沿后触发器的状态。 对于给定输入序列,重复步骤2、3、4。 2018/12/5 逻辑设计基础
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Figure 13-5: Moore Sequential Circuit to be Analyzed
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Figure 13-6: Timing Chart for Figure 13-5
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输入输出序列: X = A = B = Z = (0) 2018/12/5 逻辑设计基础
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Figure 13-7: Mealy Sequential Circuit to be Analyzed
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Figure 13-8: Timing Chart for Circuit of Figure 13-7
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13.3 状态转换表与状态转换图 建立状态转换表的方法: 列出触发器的输入方程和电路输出方程。 由触发器的输入方程导出次态方程。
得到电路的状态转换表。 注意:米利型和摩尔型的区别。 2018/12/5 逻辑设计基础
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Moore State Tables for Figure 13-5
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(b) 2018/12/5 逻辑设计基础
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Figure 13-9: Moore State Graph for Figure 13-5
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Table 13-3. Mealy State Tables for Figure 13-7
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(b) 2018/12/5 逻辑设计基础
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Fig 13-11: Mealy State Graph for Figure 13-7
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Figure 13-12a: Serial Adder
例题1--- 串行加法器 Figure 13-12a: Serial Adder 2018/12/5 逻辑设计基础
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Figure 13-13: Timing Diagram for Serial Adder
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Figure 13-14: State Graph for Serial Adder
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Table 13-4. A State Table with Multiple Inputs and Outputs
例题2 Table A State Table with Multiple Inputs and Outputs 2018/12/5 逻辑设计基础
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Figure 13-15: State Graph for Table 13-4
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例题3 Figure 13-16 2018/12/5 逻辑设计基础
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Figure 13-16 2018/12/5 逻辑设计基础
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13.4 时序电路的通用模型 图 Mealy电路通用模型 2018/12/5 逻辑设计基础
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Figure 13-18: Minimum Clock Period for a Sequential Circuit
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Figure 13-19: General Model for Moore Circuit Using Clocked D Flip-Flops
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Table 13-5 State Table with Multiple Inputs and Outputs
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