4-15 WDT HT66F50.

Presentation on theme: "4-15 WDT HT66F50."— Presentation transcript:

1 4-15 WDT HT66F50

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3 避免因不可預期因素造成系統長時間癱瘓 WDT計數時脈可為內部RC振盪器LIRC, LXT Fsys/4 清除WDT方式:外部重置信號,HALT指令,WDT清除指令

4 WDTC 控制暫存器 FSYSON WS2 WS1 WS0 WDTEN3 WDTEN2 WDTEN1 WDTEN0
Bit FSYSON: 1 , IDLE 模式時維持 Fsys 開啟 0, , IDLE 模式時關閉 WS[2:0]: WDT 計時週期選擇位元 000=WDT計時結束時間為28/fs , 100=WDT計時結束時間為212/fs 001=WDT計時結束時間為29/fs , 101=WDT計時結束時間為213/fs 010=WDT計時結束時間為210/fs ,110=WDT計時結束時間為214/fs 011=WDT計時結束時間為211/fs ,111=WDT計時結束時間為215/fs WDTEN[3:0]: WDT致能/禁能控制位元 1010關閉WDT功能

5 4-15 WDT 程式以0.25秒的速度顯示 0 – 9, 之後清除七段進入 STOP 迴圈, 1秒後自動開始執行程式
;PROGRAM:4-15.ASM (4-15.PJT) ;FUNCTION:WDT DEMO PROGRAM By Steven ; NOTE :CONFIGURATION OPTION ; WDT :ENABLE CLRWDT :ONE CLEAR INSTRUCTION ; WDT clock source fS :fSUB fSUB clock source :LIRC 32KHZ #INCLUDE HT66F50.INC ;========================================================= MY_DATA .SECTION 'DATA‘ ;==DATA SECTION== DEL1 DB ? ;DELAY LOOP COUNT1 DEL2 DB ? ;DELAY LOOP COUNT2 DEL3 DB ? ;DELAY LOOP COUNT3 COUNT DB ? ;============================================================ SEG_PORT EQU PD ;DEFINE 7-SEG PORT SEG_PORTC EQU PDC ;DEFINE 7-SEG PORT CONTROL REG 程式以0.25秒的速度顯示 0 – 9, 之後清除七段進入 STOP 迴圈, 1秒後自動開始執行程式

6 MY_CODE .SECTION AT 0 'CODE‘ ;==PROGRAM SECTION== ORG 00H ;HT-66FXX RESET VECTOR MOV A, B MOV CP0C,A ;Disable Comparator 0 Function MOV CP1C,A ;Disable Comparator 1 Function CLR ACERL ;Digital I/O Pin is assigned as a I/O line CLR SEG_PORTC ;CONFIG SEG_PORT AS OUTPUT MOV A, B ;WDT TIME-OUT PERIOD IS 2^15/fS MOV WDTC,A ;AND ENABLE WDT MAIN: MOV A,TAB_7_SEG MOV TBLP,A ;INITIAL POINTER START ADDRESS MOV A,10 MOV COUNT,A ;SET DATA COUNT OF TAB_7_SEG

7 LOOP: TABRDL SEG_PORT ;READ TABLE AND SEND TO SEG_PORT MOV A,25 ;SET DELAY FACTOR CALL DELAY ;DELAY 250mS INC TBLP ;UPDATE TABLE POINTER SDZ COUNT ;COUNT DOWN BY 1 JMP LOOP ;JUMP IF NOT TABLE END CLR SEG_PORT ;TURN OFF 7-SEG LED STOP: JMP STOP ;IDEL LOOP ;================================================================== ; PROC : DELAY ; FUNC : DEALY ABOUT ; PARA : ACC : DELAY FACTOR ; REG : DEL1,DEL2,DEL3

8 ;將CLR WDT 拿掉 七段只顯示 0-4 DELAY PROC MOV DEL1,A ;SET DELAY FACTOR
DEL_1: MOV A,30 MOV DEL2,A ;SET DEL2 COUNTER DEL_2: MOV A,110 MOV DEL3,A ;SET DEL3 COUNTER DEL_3: SDZ DEL ;DEL3 DOWN COUNT JMP DEL_3 SDZ DEL ;DEL2 DOWN COUNT JMP DEL_2 SDZ DEL1 ;DEL1 DOWN COUNT JMP DEL_1 CLR WDT ;MASK THIS LINE TO SEE DIFFERENCE RET DELAY ENDP ORG LASTPAGE TAB_7_SEG: DC 03Fh,006h,05Bh,04Fh,066h ;7 SEG CODE FOR COMMOM CATHOD LED DC 06Dh,07Dh,007h,07Fh,067h ;CONNECT BIT 0-7 FOR SEGMENT A-H END ;將CLR WDT 拿掉 七段只顯示 0-4