CEPC顶点探测器研究进展 Yang ZHOU on behalf of the VTX R&D team 2016年9月28日.

Presentation on theme: "CEPC顶点探测器研究进展 Yang ZHOU on behalf of the VTX R&D team 2016年9月28日."— Presentation transcript:

1 CEPC顶点探测器研究进展 Yang ZHOU on behalf of the VTX R&D team 2016年9月28日

2 Chip design 张颖、周扬 Second prototype design: under development; on the stage of pixel layout design. Purpose: small-size digital pixel design verification Proposed floor plan: Four 32×64 pixel array sub-matrices Two asynchronous readout mode matrix Two rolling-shutter readout mode matrix Floor plan of the second prototype (Final layout may slightly change)

3 Asynchronous readout mode digital pixel
张颖

4 Asynchronous readout mode digital pixel
张颖

5 Two versions of rolling shutter readout mode digital pixels:
周扬 Version 1: differential amplifier + latch Version 2: 2 stage CS amplifiers + latch Similar transistor numbers Version 1 has lower amplification factor while suffer less from LATCH ‘kickback noise’

6 Test system development
王娜、王科、史欣、卢小旭 To characterize the prototype from the 1st submission: basically done, on the stage of final check before fabrication

7 测试系统 适配的测试方案： 暂时不做屏蔽盒： PCIE数据传输：辅导学生接手PCIE接口数据获取工作
正面测试，支架+放射源 侧面测试，tct激光，测耗尽区厚度 暂时不做屏蔽盒： PCIE数据传输：辅导学生接手PCIE接口数据获取工作 子板—母板：长线连接（1m以上），buffer驱动 测试系统可以做总剂量抗辐射测试 以及 位移效应测 试（中子辐照）

8 Outlooks Sensor design: Test system development: Optimization;
Layout routing; TJ MPW share with IPHC and CCNU probably Feb. 2017 Test system development: Final check & Test boards fabrication; Test system development; 1st prototype sensors characterization