CoWoS ＆ Fan-Out Process Flow

Presentation on theme: "CoWoS ＆ Fan-Out Process Flow"— Presentation transcript:

1 CoWoS ＆ Fan-Out Process Flow
胡承維 2017/12/29

2 3DIC 3DIC為將許多晶片進行三維空間垂直整合 Chip TSV Underfill Solder Ball RDL PCB

3 3DIC Solder Bump:連接腳位 TSV:上下晶片訊息連結之通道 Copper piller:用來增加訊號的傳遞
Chip TSV:上下晶片訊息連結之通道 Copper piller:用來增加訊號的傳遞 Underfill:固定與保護Solder Ball RDL:調整晶片與晶片/基板間的接觸接觸腳位

4 在晶片與基板之間加入Si interposer，藉由Si interposer整合晶片並當作晶片與基板的連接橋梁。
2.5DIC 在晶片與基板之間加入Si interposer，藉由Si interposer整合晶片並當作晶片與基板的連接橋梁。 ubump Underfill TSV PCB Solder Ball Substrate

5 Packaging Technology 目前主流晶片封裝方式: CoWoS InFO Face Down(Die first)
Face Up(Die first) Face Down(Die last) InFO_PoP

6 Packaging Technology 目前主流晶片封裝方式: CoWoS(Chip-on-Wafer-on-Substrate)
InFO Face Down(Die first) Face Up(Die first) Face Down(Die last) InFO_PoP

7 CoWoS(Chip-on-Wafer-on-substrate)
CoWoS(Chip-on-Wafer-on-Substrate)是一種整合生產技術，先將晶片透過Chip on Wafer(CoW)的封裝製程連接至矽晶圓，再把CoW晶片與基板連結，整合成Chip-on-Wafer-on-Substrate。 SoC PCB HBM Wafer Substrate CoW(Chip-on-Wafer) CoWoS(Chip-on-Wafer-on-substrate)

8 CoWoS Process Flow 先將Si interposer與晶片藉由ubump堆疊至一起
Top die SoC HBM2 Cu piller Solder ball ubump:一對Cu piller中間焊Solder Si interposer Bottom die 先將Si interposer與晶片藉由ubump堆疊至一起 填入Underfill保護晶片與連結的結構

9 CoWoS 製程 將晶片接合至載板 (連接到載板主要是為了方便後面製程進行)
carrier 進行化學機械平坦化製成(CMP)將Si interposer薄化 carrier 加入RDL與Solder ball carrier

10 CoWoS 製程 將晶圓從載板轉移至膠帶上 切割晶圓 (以上製程皆是wafer，直到此製程才切割成chip)
將晶片從膠帶上取下並結合至基板上 PCB

11 CoWoS 製程 熱介面金屬 最後加上保護封裝體之環形框和蓋板並使用熱介面金屬(TIM)填補與蓋板接合時所產生的空隙。 PCB

12 Homogeneous Integration
Dimension of CoWoS uBump (die:20um) (pitch:45um) FPGA (size:7x23mm2) TSV (die:12um) (pitch:180um) C4bump (die:80um) (pitch:180um) PCB Substrate (size:42.5x42.5mm) Homogeneous Integration BGA (pitch:100mm)

13 CoWoS 的發展 隨著效能的需求，CoWoS的Si interposer面積近幾年來不斷增加

14 First-Generation of CoWoS
In 2012, TSMC successfully used CoWoS® to integrate four 28nm logic chips。 Homogeneous and heterogeneous interposer up to 800 mm2 (Full reticle size) Homogeneous Integration (ex:Split Logic) Heterogeneous Integration (Logic + DRAM)

15 Second-Generation of CoWoS
第二代CoWoS為將Si interposer擴增到1200mm2並結合fine pitch Cu bump, HBM2 integration, and HD-MIM capacitors 使其有更好的效能。 Interposer size:1200m2 PCB

16 Second-Generation of CoWoS
Mask Stitching Technology: 由於Si interposer增加到1200mm2，利用此技術將兩個光罩縫合製造出更大的光罩以應用在Second-Generation CoWoS上。 由左圖可知，在縫合後的光罩所製造出來的RDL與一般無縫合的光罩所製造出來的RDL其片電阻是幾乎相同的。 Rs of normal and stitched 0.4/0.4 μm width/space RDL in ultralarge Si interposer.

17 Second-Generation of CoWoS
Fine Pitch Cu Bump:藉由良好的間格和Cu bump與無鉛的銲錫連接，可以減少傳統C4 solder bump的bump bridge 問題。 C4 Cu bumps at interposer corners remain undistorted after flip-chip bond process on a substrate. Cu bumps traditional solder bumps X-Ray images of CoWoS package

18 Second-Generation of CoWoS
Integration of HD-MIM(High Density-Metal Insulator Metal) Capacitors: 藉由在Si Interposer中用HD-MIM電容可以有供應的穩定電壓與減少電源處傳來的雜訊。 Integration of HBM2: HBM2提供更大的密度與頻寬。

19 Nvidia GP100 Interposer (Area:1200mm2) HBM2 (size:8x12x0.72mm)
uBump(for HBM2) (pitch:96/55um) PCB Substrate (size:55x55x1.2mm) BGA (pitch:100um)

20 About CoWoS Application of CoWoS : AI Server Networking
Characteristic of CoWoS : Ultra-high performance, SoC partition Very high memory bandwidth Wide envelope

21 Strengths of CoWoS Fine RDL pitch & High TSV density Si interposer
Fine pitch Micro-bump Assembly Fine gap Flip Chip underfill CoW warpage control Large die reliability

22 Packaging Technology 目前主流晶片封裝方式: CoWoS(Chip-on-Wafer-on-Substrate)
InFO(Integrated Fan-Out) Face Down(Die first) Face Up(Die first) Face Down(Die last) InFO_PoP

23 InFO Process Flow(Face Down)
Chip 將晶片切割且用膠帶黏在載板上 carrier 利用compression molding method 建造環氧模壓樹脂 (EMC)的模封 carrier 從膠帶上取下

24 InFO Process Flow(Face Down)
加上RDL與錫球，封裝完成!

25 Packaging Technology 目前主流晶片封裝方式: CoWoS(Chip-on-Wafer-on-Substrate)
InFO(Integrated Fan-Out) Face Down(Die first) Face Up(Die first) Face Down(Die last) InFO_PoP

26 InFO Process Flow(Face Up)
Chip 將晶片切割且用膠帶黏在載板上 carrier 利用compression molding method 建造環氧模壓樹脂 (EMC)的模封 carrier 進行化學機械平坦化製成(CMP)將模封薄化 carrier

27 InFO Process Flow(Face Up)
加上RDL與錫球 carrier 去除載板 完成!

28 Face up versus Face down
Face up多了一步CMP製程，製程花費相對較高，但Face down在取掉carrier並加上RDL的製程因會有翹區現象產生所以相當困難 carrier carrier carrier carrier CMP carrier carrier 容易有翹曲現象產生

29 Packaging Technology 目前主流晶片封裝方式: CoWoS(Chip-on-Wafer-on-Substrate)
InFO(Integrated Fan-Out) Face Down(Die first) Face Up(Die first) Face Down(Die last) InFO_PoP

30 InFO Process Flow(Die Last)
Apply release layer on carrier RDL on the carrier carrier Face-down attach carrier Molding carrier

31 InFO Process Flow(Die Last)
Carrier remove Solder ball attach

32 Dimension of InFO RDL (w/s:5um/5um) 250um BGA (H:190)

33 About InFO Application of InFO : Smart mobile(Apple A10 Fusion) IoT
HPC Characteristics of InFO : Multi-chip Integration Small form-factor Cost competitive

34 Strengths of InFO Compared with Flip-Chip, InFO provides :
Low Power consumption High Performance Smaller thickness Competitive cost

35 Packaging Technology 目前主流晶片封裝方式: CoWoS(Chip-on-Wafer-on-Substrate)
InFO(Integrated Fan-Out) Face Down(Die first) Face Up(Die first) Face Down(Die last) InFO_PoP(Integrated Fan-Out_Package-on-Package)

36 InFO＿PoP Process Flow Pick&Place the chip on the carrier
Molding Compound Cu-RDL and BGA

37 InFO＿PoP Process Flow De-bound Packaging & Stacking Dicing & shipping
TIV :which is the InFO-PoP version of a through-silicon via (TSV), used with 3D silicon interposer technology. De-bound Packaging & Stacking Memory SoC Dicing & shipping TIV