Progress Report Yuan-Hsin Liao 10/22/2014.

Presentation on theme: "Progress Report Yuan-Hsin Liao 10/22/2014."— Presentation transcript:

1 Progress Report Yuan-Hsin Liao 10/22/2014

2 DVC Encoder Architecture
External SRAM

3 QCIF Mode Timing System clock: 50 MHz Sensor clock: 25 MHz FPS: 145

4 CIF/4CIF Mode Timing WZ fails at CIF and 4CIF mode
data flow problem, use invalid data from memory, cause SPI ouput turn out unknown signal

5 RS9110-N-11-02 (REDPINE SIGNALS)
Specification (1/2) QCIF 4CIF Process TSMC 90nm Working Frequency 50 MHz Mode Resolution 176x144 704x576 Throughput 30 fps 15 fps On-Chip Memory Input buffer 2*SRAM_DP_128x32 2*SRAM_DP_176x32 Original frame buffer SRAM_SP_16384x32 RF_SP_64x32 Reconstruct wifi SRAM_DP_1024x32 wz_ctrl SRAM_DP_512x32 SRAM_DP_2048x64 wz_enc SRAM_DP_128x32 2*SRAM_DP_1584x32 h264_enc RF_SP_32x32 SRAM_DP_160x32 2*SRAM_DP_192x32 RF_SP_80x16 RF_SP_80x8 SRAM_SP_640x32 RF_SP_160x20 External Memory IS61WV51232 FPGA Altera Cyclone IV EP4CE115 Sensor OV7670 (OmniVision) EEPROM Microchip 24AA02/24LC02B WIFI RS9110-N (REDPINE SIGNALS) Gate Count Power Area

6 Specification (2/2) Name Width Type clk 1 Input rst_n rst_camera_n
dbg_uart_tx Output dbg_uart_rx eeprom_scl eeprom_sda Inout wifi_rst_n wifi_intr wifi_spi_clk wifi_spi_cs_n wifi_spi_mosi wifi_spi_miso cam_scl cam_sda cam_xclk cam_pclk cam_vsync cam_href cam_pixel [7:0] 8 extsram_ce_n extsram_oe_n extsram_we_n extsram_bwa_n extsram_bwb_n extsram_bwc_n extsram_bwd_n extsram_addr[18:0] 19 extsram_dq[31:0] 32 inout GPI [17:0] 18

7 Schedule Deadline Item Status 10/3 讓現有的QCIF版本的RTL code可以合成 Closed
重現FPGA驗證環境 10/10 10/21 更改規格 QCIF -> 4CIF: 目前架構經過評估無法進行FPGA驗證，需要更改架構 改成用external SRAM架構: WZ在開到CIF/4CIF mode的時候會fail Open 加入內建的test pattern DVC軟體解不出來 Abort Try run synthesis and APR Synthesis: done APR: open 10/15 FPGA驗證 for QCIF 修改後的版本已驗證沒問題 FPGA驗證 for 4CIF FPGA內建的SRAM太小無法驗證 Try run post simulation 10/23 Synthesis and APR 10/24 Post simulation Tapeout