Arithmetic for Computers Chapter 3 Arithmetic for Computers 電腦之算術運算 ROBERT CHEN

Outlines Signed and Unsigned Numbers(有號數與無號數) Addition and Subtraction(加法與減法)) Multiplication(乘法) Division(除法) Floating Point(浮點數)

Signed and Unsigned Numbers Numbers can be presented in any base(基底) A n-bit number: an-1an-2…a1a0, base is d, then its decimal value is: an-1× d n-1+ an-2 × d n-2 + … + a1 × d n-1 + a0 × d 0 (10) Where a0 called the Least Significant Bit (LSB最低有效位元), an-1 called the Most Significant Bit (LSB最高有效位元) [Ex] 1011two = ten ? [Ans] (1 × 23) + (0 × 22) + (1 × 21) + (1 × 20) = (1 × 8) + (0 × 4) + (1 × 2) + (1 × 1) = 8 + 0 + 2 + 1 = 11ten

Signed and Unsigned Numbers Negative Number Representation (負數表示法) Sign-magnitude 1’s complement 2’s complement (adopted by all now-a-day computers) For a n-bit binary number The Most Significant Bit (MSB) represents the sign : 0 : positive, 1:negative The rest (n-1) bits represents the magnitude Method comparison SM 1’s 2’s Positive number(正數) sm Negative number(負數) sm’ s(m’+1) Range -(2n-1-1) ~ +(2n-1-1) -(2n-1) ~ +(2n-1-1) Zero representation +0, -0 +0 快速求法：欲求某負數之2’s complement表示法，可先求其正數，再取補數後加1，注意位元數目！

Signed and Unsigned Numbers Three presentations for a 4-bit number Signed number Sign-Magnitude sm 1’s complement sm’ 2’s complement s (m’+1) Biased notation comments +7 0111 1111 7 Positive number: all the same +6 0110 1110 6 +5 0101 1101 5 +4 0100 1100 4 +3 0011 1011 3 +2 0010 1010 2 +1 0001 1001 1 +0 0000 1000 -0 (1000) = -8 -1 Negative number 2’s complement has no negative zero and 1000 represents -810 -2 -3 -4 -5 -6 -7 -8

Unsigned Sign-magnitude 1’s complement 2’s complement Excess-8 0000 +0 -8 0001 1 +1 -7 0010 2 +2 -6 0011 3 +3 -5 0100 4 +4 -4 0101 5 +5 -3 0110 6 +6 -2 0111 7 +7 -1 1000 8 -0 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 Positive number M sm s’m (2n-1+m) Negative number -- sm’ s(m’+1) s’(m’+1) range 0 ~ +(2n-1-1) -(2n-1-1) ~ +(2n-1-1) -(2n-1) ~ +(2n-1-1) usage comparison invert addition

Signed and Unsigned Numbers 2’s complement binary number to decimal conversion an-1× (-d n-1)+ an-2 × d n-2 + … + a1 × d n-1 + a0 × d 0 (10) [Ex] what is the decimal number of the 32-bit binary pattern? 1111 1111 1111 1111 1111 1111 1111 11002 [Ans] (1×-231) + (1×230) + (1×229) + … + (1×22) + (0×21) + (0×20) = - 231 + 230 + 229 + … + 22 + 0 + 0 = - 214748364810 + 214748364410 = - 410 [Ex] Find -210 2’s complement representation Find 210 = 0000 0000 0000 0000 0000 0000 0000 00102 Complement : 1111 1111 1111 1111 1111 1111 1111 11012 Add 1 : 12 1111 1111 1111 1111 1111 1111 1111 11102 ＋

Signed and Unsigned Numbers [Ex] Show that a 2’s-complement number can be converted to a representation with more bits by sign extension. That is, given an n-bit 2’s-complement number X, show that the m-bit 2’s-complement representation of X, where m > n, can be obtained by appending m-n copies of X’s sign bit to the left of thze n-bit representation of X. [84清大電機] [Ans] 若假設X為n-bit正數，欲做sign extension成A (m-bit)，則將bit n~(m-1)補0，則 若假設X為n-bit負數，欲做sign extension成A (m-bit)， 因為轉換後的A=原來的X值，所以 明顯地，ai(n-1  i  m-2)必須全為1，亦即將an-1=1做sign extension （因為am-1 ~ an-1皆為0） n-1 m-1 n bits m-n bits

Signed and Unsigned Numbers [Ex] Let A=an-1an-2…a1a0 be a two’s complement integer. Show that [Ans] (1)若A為正數，則an-1=0，A=an-1an-2…a1a0(2)=0an-2…a1a0(2)= (2)若A為負數，則an-1=1，A=an-1an-2…a1a0(2)=1an-2…a1a0(2) 由(1),(2)得證

Signed and Unsigned Numbers Sign extension (符號擴展) Converting n-bit numbers into numbers with more than n bits copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 MIPS “data transfer” instruction (load/store) Load word lw $s1, 100($s2) $s1 = M[$s2+100] Mem.  Reg. Store word sw $s1, 100($s2) M[$s2+100] = $s1 Reg.  Mem. Load unsigned half word lhu $s1, 100($s2) Store half word sh $s1, 100($s2) Load unsigned byte lbu $s1, 100($s2) Store byte sb $s1, 100($s2) Load upper half word immediate lui $s1, 100 $s1 = 100 * 216

Signed and Unsigned Numbers Signed vs. unsigned number $s0 = 1111 1111 1111 1111 1111 1111 1111 11112 $s1 = 0000 0000 0000 0000 0000 0000 0000 00012 slt $t0, $s0, $s1 # signed number comparison sltu $t1, $s0, $s1 # unsigned number comparison After executing the above instructions, $t0 = 1, $t1 = 0. Why? Range detection [Ex] If ($a1>$a2) or ($a1< 0) then jump to IndexOutOfBounds sltu $t0, $a1, $t2 # temp reg $t0=0, if k>=length or k<0 beq $t0, zero, IndexOutOfBounds # if exceed, then jump

Signed and Unsigned Numbers [Ex1] Write all 4-bit numbers using the above representations. (1) according the decimal number (2) according the 0000 ~ 1111 (3) compare their range and zero representation,  max/min number [Ex2] Show -18 using the above representations with (1) 8 bits (2) 16 bits. [Ans] sign-magnitude: 10010010 1000 0000 0001 0010 1’s complement: 11101101 1111 1111 1110 1101 2’s complement: 11101110 1111 1111 1110 1110 [Ex3] Why 2’s complement representation is better than the others in computer architecture? [Ans] 1. One representation of zero 2. Arithmetic works easily 3. Negating is fairly easy [Ex4] What is overflow ? How to judge whether an overflow happens or not? Cin  Cout =1 [Ex5] Express +69 and -69 with 8 bits using signed-magnitude, 1’s complement, 2’s complement and excess code representations. [Ans] sign-magnitude 0100 0101 1100 0101 1’s complement 0100 0101 1011 1010 2’s complement 0100 0101 1011 1011 excess-128 code 1100 0101 0011 1011

Overflow Overflow(溢位) 意義：兩數做算術運算，其結果超出其所能表示之範圍 e.g., adding two n-bit numbers does not yield an n-bit number 0111+0001 可能發生之狀況： 正數＋正數 正數－負數 負數＋負數 負數－正數 判斷是否發生溢位 MSB之Cin  Cout = 0 表無溢位：將進位捨棄，結果為正確答案 MSB之Cin  Cout = 1 表有溢位：結果為錯誤答案 解決溢位之方法 增加位元數目 1 1 1 1 0 進位 0 1 1 1 + 0 0 0 1 1 1 0 0 0 MSB Cin Cout 進位

Effects of Overflow An exception (interrupt) occurs Control jumps to predefined address for exception Interrupted address is saved for possible resumption Don't always want to detect overflow addu, addiu, subu do NOT cause exceptions on overflow note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons add, addi, sub cause exceptions on overflow MIPS C compiler 總是產生無號數之算術指令所以會忽略溢位，但MIPS FORTRAN compiler則會依據運算元型態產生適當的算術指令 自行研究課本p.173,174之程式

Review: ALU Design 建立算術邏輯單元 由建立一個位元的算術邏輯單元 (ALU)開始, 因為MIPS的字組都是32位元的長度，所以的ALU也必須是32位元 使用 4 種基本硬體元件來建構ALU

Review: ALU Design 一位元加法器(Full Adder全加器) a + b 輸入 輸出 Sum CarryIn 1 b CarryIn Sum CarryOut 輸入 輸出 + a b Sum CarryIn CarryOut

Review: ALU Design 一位元ALU 執行 AND， OR及加 由32個一位元 ALU所建構的一個32位元的ALU 運算 = 位元2 為加法的運算結果 由32個一位元 ALU所建構的一個32位元的ALU

Review: ALU Design 減法如同對運算元的反相值做加法運算而且最低有效位元(LSB)本身還是有個進位輸入訊號(CarryIn) a + (¬b) + 1 = a + (-b) = a - b 一位元 ALU 執行 AND, OR及對 a 和 b 或 a 和 ¬b 做加法運算及減法運算 ALU 0: Operation = 2, Binvert = 1, 及 CarryIn = 1 ALU 1-31: Operation = 2 及 Binvert = 1

Review: ALU Design 支援小於即設定 (slt)指令 範例： slt $t0, $s1, $s2 ai：暫存器 $s1的位元 i bi：暫存器$s2的位元 i 結果： 假如 $s1 < $s2 0…001 否則 0…000

Review: ALU Design 32位元 ALU 觀察：假如 $s1 - $s2 <0, 則 $s1 < $s2 結果 0 = 加法器的符號位元 控制訊號 / 輸入 Operation = 3 Less 1-31 = 0 Binvert = 1 CarryIn 0 = 1 Less 0 = Set

Review: ALU Design 32位元ALU(續) 設定 Binvert = 1 及 CarryIn 0 = 1做減法運算 組合 Binvert 及CarryIn 0 為一條控制線，稱為 Bnegate (下一頁之圖)

Review: ALU Design 支援條件分支指令 假使兩個暫存器相等或假使不相等時作分支 觀察 Zero = 0 不等時 if a=b then a-b = 0 if a-b = 0 then Result = 0…00 Zero = 0 不等時 Zero = 1 相等時

Review: ALU Design 常用來直接代表 ALU的符號 ALU控制線的值 及相對應的功能 Bnegate 1 Operation 1 Operation 00 01 10 11 and or add subtract set on less than 功能

Review: ALU Design We can build an ALU to support the MIPS instruction set key idea: use multiplexer (MUX) to select the output we want efficiently perform subtraction using two’s complement replicate a 1-bit ALU to produce a 32-bit ALU Important points about hardware all of the gates are always working the speed of a gate is affected by the number of inputs to the gate the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”)

Parallel Adder vs. Carry Look Ahead Adder Half adder (HA) 2 bits adder, say x and y Sum = x  y Carry = xy Full adder (FA) 3 bits adder, say x, y and c Sum = x  y  c Carry = (x  y) c + xy Propagation delay time tp(net) = tXOR+max(tXOR, 2tNAND) N-bit parallel adder can be implemented by n FAs Propagation delay time: tp(net) = (n-1) tc+max(ts, tc) tp , ts , tc : propagation delat time of the total path, the sum and the carry, respectively. FAn-1 FAn-2 FA1 FA0 x0 y0 s0 x1 y1 s1 xn-2 yn-2 sn-2 xn-1 yn-1 sn-1 c0 c1 cn-2 cn-1 cn Each FA is a two-level logic circuit, if the propagation delay time of one two-level logic circuit is d, then that of a n-bit parallel adder is nd.

Parallel Adder vs. Carry Look Ahead Adder Ripple Carry Adder (Parallel adder) 8 bits binary adder-subtractor Each full adder has a small propagation delay; these delays add up as the carry bits are propagated.

Computer Organization & Design 3rd. Parallel Adder vs. Carry Look Ahead Adder Carry Lookahead Adder (4 bits) One solution to the delay problem The generate part ,g, g = X  Y (carry generator) The second part is the propagate, p, p = X  Y (carry propagation) In general, this can be expressed by the equation Si = Pi  Ci Ci+1 = gi + piCi For the 4-bit adder, these values are

Computer Organization & Design 3rd. Parallel Adder vs. Carry Look Ahead Adder Carry Lookahead Adder Block diagram g0 p0 g1 p1 g2 p2 g3 p3 C0 X0 Y0 X1 Y1 X2 Y2 X3 Y3 S0 S1 S2 S3 C4 C1 C2 C3 74182

Parallel Adder vs. Carry Look Ahead Adder [Ex1] If the propagation delay time of S is 30ns and that of C is 20ns in an FA. What is the total propagation delay of a 4-bit ripple carry adder (7483)? KEY: Calculate the longest path 30 +20 x (4-1) = 90 ns [Ex2] Repeat [Ex1] for a 32-bit ripple adder, the propagation delay time is ________. 30+ 20(32-1) =650ns [Ex3] If the propagation delay time of a lookahead carry generator is 20ns, that of pi and gi is 20ns. What is the total propagation delay of a carry lookahead adder ? 40ns (see Fig. on page 4-7) [Ex4] Repeat [Ex1] for a 32-bit carry lookahead adder , the propagation delay time is ________. 40ns The propagation delay time of look-ahead adder is independent of . FAn-1 FAn-2 FA1 FA0 x0 y0 s0 x1 y1 s1 xn-2 yn-2 sn-2 xn-1 yn-1 sn-1 c0 c1 cn-2 cn-1 cn

Multiplication Unsigned Integer multiplication(無號整數相乘) 範例 ． Example. 1000 x 1011 1000_ 0000__ 1000___ 1011000 Example. (0010)2 x (0011)2: 0010 x 0011 0010_ 0000__ 0000___ 0000110 multiplicand被乘數 multiplier乘數

Multiplication First version Product register is initialized to 0 1 . T s t M u l i p r a A d m c h P g 2 S f b 3 ? = N : < Y First version Product register is initialized to 0 It takes almost 100 clock cycles, if each step took a clock cycle

Multiplication Example for first-version multiplier f Using 4-bit number, multiply 210 × 310 = 00102 × 00112

Computer Organization & Design 3rd. Multiplication D o n e 1 . T s t M u l i p r a A d m c h f P g 2 S b 3 ? = N : < Y Sequential (second) version multiplier Product register is initialized to 0 32-bit ALU

Multiplication Example for sequential-version multiplier f Using 4-bit number, multiply 210 × 310 = 00102 × 00112

Multiplication Final (third) version multiplier 32-bit ALU Product register right half is initialized to the value of multiplier 60 clock cycles

Computer Organization & Design 3rd. Multiplication Signed Multiplication(有號數乘法) Convert the multiplier and multiplicand to positive numbers and remember the original signs. Shifting steps need to extend the sign of the product Negate the product if the original signs disagree. [NOTE] 有號數乘法：利用第三版乘法器先做前面31位元的運算，再比較乘數及被乘數的符號(第32位元)是否相同 A more elegant method: Booth’s algorithm 對有連續1的乘數可加速處理 碰到第一個1加法變減法

Computer Organization & Design 3rd. Booth’s Algorithm Classifying groups of bits into the beginning, the middle or the end of a run of 1s Take a look at 2-bit groups 1 Middle of Run End of Run Beginning of Run

Computer Organization & Design 3rd. Booth’s Algorithm Depending on the current and previous bits, do one of the following: 00: no arithmetic operation 01: End of a string of 1s, so add multiplicand to the left half of the product 10: Beginning of a strings of 1s, so subtract the multiplicand from the left half of the product 11: no arithmetic operation Shift the Product register right 1 bit.

Computer Organization & Design 3rd. Booth’s Algorithm Example 2 x (-3) = 6 or 0010 x 1101 = 1111 1010 Iteration Step Multiplicand Product Initial values 0010 0000 1101 1 1c: 10=>P-M 1110 1101 2 : Shift right P 1111 0110 2 1b: 01=>P=P+M 0001 0110 0000 1011 3 1110 1011 1111 0101 4 1d: 11=> no operation 1111 1010 Current bit Previous bit

Booth’s Algorithm Multiply by 2 i via shift Shift left by one bit --> multiply by 2 Shift left by n bit --> multiply by 2 n Proof of Booth’s Algorithm Why does it work for 2’s complement signed number? In other words, if (ai-1 - ai) = 0 do nothing = 1 add b = -1 subtract b Booth’s algorithm can be written as: (a-1 - a0) x b x 2 0 + (a0- a1) x b x 2 1 + … +(a30-a31)x b x 2 31 = … = b x a

整數的乘法 前提 布斯演算法 所有數值均以2補數法表示 被乘數乘數=乘積 (multiplicand  multiplier = product) (n bits)  (n bits) = (2n bits) : 若不足位需做符號擴展 被乘數需一個n bit的暫存器，乘積需一個(2n+1) bit的暫存器，但乘數置於乘積的左半部 多那一個bit….要做啥？(輔助位元) 布斯演算法 取決於乘數中前一個與目前bit(從後面來)，並依下列情況處理: 00: 不做算術運算，乘積右移一位 01: 連續字串1的結尾，將被乘數加到乘積左半邊中，乘積右移一位 10:連續字串1的開始，從乘積左半邊減去被乘數，乘積右移一位 11: 不做算術運算，乘積右移一位

整數的乘法 布斯演算法範例 (4 bits) 2 x (-3) = -6 or 0010 x 1101 = 1111 1010 密技1: A-B = A+(-B) =A+(B’+1) 密技2: 採用算術右移，符號 位元保持不變 整數的乘法 布斯演算法範例 (4 bits) 2 x (-3) = -6 or 0010 x 1101 = 1111 1010 Iteration Step Multiplicand Product 初始值 0010 0000 1101 1 1c: 10 => P左=P左-M 1110 1101 0 ＊ 2 : Shift right P 1111 0110 2 1b: 01 => P左=P左+M 0001 0110 0000 1011 3 1110 1011 1111 0101 4 1d: 11=> no operation 1111 1010 Current bit Previous bit

Faster Multiplication Computer Organization & Design 3rd. Faster Multiplication Use 32 adders instead of using a single 32-bit adder on at a time.

Computer Organization & Design 3rd. Division Some definitions: Dividend(被除數), Divisor(除數), Quotient(商數), Remainder(餘數) Dividend = Quotient × Divisor + Remainder Example: 1001010 divided by 1000 1001 Quotient(商) Divisor 1000 1001010 Dividend(被除數) –1000 10 101 1010 –1000 10 Remainder (or Modulo result)

Computer Organization & Design 3rd. Division D o n e T s t R m a i d r 2 . S h f Q u g l , w b 1 3 v p ? < N : Y y c A > First version Divisor 6 4 - b i t A L U C o n r l e s Q u S h f R m a d W D v g 3 2

Computer Organization & Design 3rd. Example Using a 4-bit version to perform 7  2 = 3…1 Iteration Step Quotient (Q) Divisor (D) Remainder (R) Initial values 0000 0010 0000 0000 0111 1 1: R=R-D (R=R+D’+1) 1110 0111 2b : Rem<0  R=R+Div, sll Q, Q0=0 3 : srl Q 0001 0000 2 1: R=R-D 1111 0111 0000 1000 3 1111 1111 0000 0100 4 0000 0011 2a : Rem  0,sll Q, Q0=1 0001 0000 0010 5 0011 0000 0001

Division Observations on the first version of the division hardware 1/2 bits in divisor always 0 1/2 of 64-bit adder is wasted 1/2 of divisor is wasted Instead of shifting divisor to right, shift remainder to left? 1st step cannot produce a 1 in quotient bit (otherwise too big) switch order to shift first and then subtract, can save 1 iteration

Computer Organization & Design 3rd. Division Second Version of the division hardware C o n t r l e s Q u i S h f W 3 2 b 6 4 D v - A L U R m a d

Computer Organization & Design 3rd. Division D o n e . S h i f t l a R m d r g 1 b T s 3 , w 2 p ? < N : Y v u y c A > Final Version of the division hardware Execute 7  2 = 3…1 using the algorithm (DIY) W r i t e 3 2 b s 6 4 S h f l g R m a n d - A L U D v o C

Computer Organization & Design 3rd. Division Signed Division(有號數除法) Dividend = Quotient * Divisor + Remainder Consider the signs of dividend and divisor : 7  2 +7  +2 = +3 … +1  7 = (+3) × 2 + 1 -7  +2 = (-3) … (-1)  - 7 = (-3) × 2 + (-1) +7  -2 = (-3) … +1  7 = (-3) × (-2) + 1 -7  -2 = +3 … (-1)  - 7 = (+3) × (-2) + (-1) Correctly signed division algorithm If the signs of the operands are opposite negative the Quotient make the sign of the nonzero Remainder match the Dividend 除法運算元異號時，商數取負號，非零餘數與除數同號

Computer Organization & Design 3rd. Floating Point IEEE754 表示形式：(-1)s × (1.m) * 2e 格式： Single precision (單精度): 4 bytes : (S,E,M) = (1, 8, 23) ,指數: 超27-1 Double precision (倍精度): 8 bytes : (S,E,M) = (1, 11, 52) ,指數: 超210-1 ？？ precision (雙倍精度): 16 bytes : (S,E,M) = (1, 15, 112) ,指數: 超214-1 轉換步驟(單精度) 轉換成二進位數(-1)s × (1.m) * 2e E = e + 127 = 2 （轉成二進位，一定只有8bits） 寫答案(SEM)

數值表示(Numeric Representation) 浮點數表示法： (Floating-point representation) 一般表示法: IEEE754表示法: IEEE754 表示形式：(-1)s × (1.m) * 2e 格式： Single precision (單精度): 4 bytes : (S,E,M) = (1, 8, 23) ,指數: 超 (27-1) Double precision (倍精度): 8 bytes : (S,E,M) = (1, 11, 52) ,指數: 超 (210-1) ？？ precision (雙倍精度): 16 bytes : (S,E,M) = (1, 15, 112) ,指數: 超 (214-1) 轉換步驟(單精度) 一律先以正數轉換成二進位數 (1.m) * 2e E = e + 127 = 2 （轉成二進位，一定只有8bits） 寫答案(SEM)，此時才依據正負號填入S 轉成十六進位

浮點數範例 [範例]用IEEE754浮點數表示-10.0312510，格式為(S,E,M)=(1,8,23) 解答: 一律先以正數轉換成二進位數 10.03125 10= 1010.000012 = 1.0100000123 (這時還不要加負號) m=010000010…0 , (共15個0) e = 3 2. E = e + (28-1-1) = 2 （轉成二進位，一定只有8bits） E = 3 + 127 = 130 10 = 10000010 2 3. 寫答案(SEM)，此時才依據正負號填入S S E M 1 10000010 010000010000…0 (共12個0) 4. 轉成十六進位 110000010 010000010000…0 2 = C120800016 Youtube影片 IEEE754轉換

Computer Organization & Design 3rd. Floating Point IEEE single presion 欄位 項目 S E M 表示大小 最大正數 11111110 111…111 + (2-2-23) × 2127 (註1) 最小正數 00000001 000…000 + 1.0 × 2-126 最大負數 1 - 1.0 × 2-126 最小負數 - (2-2-23) × 2127 00000000 0 :所有位元皆為0  0/1 11111111 ： NaN 任何非0值 無法表示之值 Not a Number 去標準化 denormalized  0.m ×2-126 (註2) 註1: 0.12 = 0.510 = 1 – 2-1 0.112 = 0.2510 = 1 – 2-2 0.11112 = 0.12510 = 1 – 2-3 註2: 0 00000000 100…0 = 0.1 × 2 -126 S E M

Floating Point Addition Computer Organization & Design 3rd. Floating Point Addition Decimal example: 9.999x101 + 1.610x 10-1 Assume 4 decimal digits of significand (有效數字) and two of exponent Algorithm Step 1: Align the decimal point (of the number of the smaller exponent) Step 2: Add significands Step 3: Convert to normalized form, check for underflow or overflow Step 4: Round the resulting significand

Floating Point Addition Computer Organization & Design 3rd. Floating Point Addition [Ex] 0.5(10) + (-0.4375)(10) [ANS] 0.5 = 1.000 × 2-1 -0.4375 = -1.110 × 2-2 Step 1: align the smaller number -1.110 × 2-2 = -0.110 × 2-1 Step 2: add the significands 1.000 × 2-1 + (-0.110 × 2-1) = 0.001 × 2-1 Step3. normalize the sum, check O/U? (1) 0.001 × 2-1 = 1.000 × 2-4 (2) 127  -4  -126  No O/U Step4: round the sum 1.000 × 2-4 = 0.000100002 = 0.062510

Floating Point Addition Computer Organization & Design 3rd. Floating Point Addition

Floating Point Multiplication Computer Organization & Design 3rd. Floating Point Multiplication Algorithm Step 1: Add the exponent (then -127 since bias is counted twice) Step 2: Multiply the two significands Step 3: Normalized the result, check for underflow or overflow Step 4: Round the resulting significand Step 5: Determine the sign

Floating Point Multiplication Computer Organization & Design 3rd. Floating Point Multiplication [Ex] 0.5(10) × (-0.4375)(10) [ANS] 0.5 = 1.000 × 2-1 -0.4375 = -1.110 × 2-2 Step 1: add the exponents (-1) + (-2) = -3 E = -3 +127 = 124 = Step 2: multiply the significands 1.000 × 1.110 = 1.110000 × 2-3 Step 3. normalize the product, check O/U? (1) 1.110 × 2-3 (2) 127  -3  -126  No O/U Step 4: round the product 1.110 × 2-3 Step 5: check the signs of operands  different -1.110 × 2-3 = -0.00111 = -0.21875

Floating Point Rounding(捨位) Computer Organization & Design 3rd. Floating Point Rounding(捨位) 計算浮點運算，其結果通常不等於真實結果。例如，0.1001 × 0.1101 = 0.01110101。但是當精確度只有5位時，則結果將為0.01110或0.01111。該如何選擇即為「捨位法」 Round to nearest 如上例，若選0.01110，則誤差為0.000000101 若選0.01111，則誤差為0.00000011 若誤差相同時 Choose the ‘even’ result. (IEEE standard!!) Round to nearest or even!!

狀態暫存器又稱為旗標暫存器(Flag) ，重要的一般旗標如下: S:符號/正負號(Sign) ，S=0表正，S=1表負 C:進位(Carry) ，最高有效位元(msb)之進位 O:溢位(Overflow) ，msb之CinCout， O=0表結果正確，O=1表錯誤 P:同位位元(Parity) ，CPU內部採奇同位 A:輔助旗標(Auxiliary) ，low-order nibble之進位 Z:零期標(Zero) ， Z=0表表運算結果不為0 ，Z=1表運算結果為0 [範例]執行 11011011 + 10101101 ，SCOPAZ=？ 111111110 11011011 10101101 110001000 Cout Cin S=1 C=1 O=CinCout=1 1=0 (奇1得1) P=1 A=1 Z=0 (結果不為0)  C S