SoC Final Project -JPEG Encoder Team 1 D90522024 劉志鵬 R91522803 鍾書耘 R91522810 張明輝
Outline Explain DCT for MYIP.v HW / SW Partition Modify Program Lifting Scheme BinDCT MYIP.v HW / SW Partition Modify Program HW / SW 1D_DCT Compressed Image File Conclusion & Future work
Explain DCT for MYIP.v Lifting Scheme BinDCT MYIP.v
Lifting Scheme Predict：使用一個input sample 去預測另一個，計算出剩餘值。 T0=X0-P．X1 Update：用剩餘值去update 原先的input sample。 T1=X1+ U．T0 Scaling：調整Predict 與Update 後的輸出值。 Y0=K0．T0 Y1=K1．T1 [1]
Lifting Scheme 所有Predict與Update的步驟都是2 冪次倒數的線性組合，只要加法與移位即可實做之。 在上圖中，不會找到Scaling這個步驟，因為BinDCT 把這個步驟並到JPEG編碼流程的Quantization 上，
BinDCT The BinDCT is an approximation of the DCT. It works only with integer numbers. its set of operations is restricted to sums and shifts. the BinDCT algorithm is used and implemented in hardware through the Verilog HDL hardware description language. [2]
BinDCT BinDCT algorithm uses a finite-state machine with a reduced number of states. Thereby, a 9-state machine was achieved, with 8 computation states and one initialization state. [2]
MYIP.v
MYIP.v
MYIP.v
HW / SW Partition Hardware [3]
Modify Program Before.cpp delete “SW” DCT_1D function call “HW” DCT_1D function (driver.cpp)
Modify Program MYIP.v
HW / SW 1D_DCT Hardware Software
Compressed Image File bmp(192KB) sw_jpeg(13.3KB) hw_jpeg(8.24KB)
Conclusion & Future work 已成功的將助教所給的code，完整的實現出來，但對於其顯示之結果，仍有相當值得存疑的部分，在書面報告中會針對此一部份特別列出加以討論分析。 期望能在下週前，將ASIC實驗中RGBtoYUV硬體實現的部分，加入final project中。
Reference [1]http://access.ee.ntu.edu.tw/course/VLSI_SP_89second/student/Final_Project/R89921046_report.pdf [2] Gustavo André Hoffmann; Eric Ericson Fabris; Diogo Zandonai; Sergio Bampi, “The BinDCT processor”, UFRGS Federal Univ. – Microelectronics Group Caixa Postal 15064 91501-970 Porto Alegre, Brazil. [3] http://access.ee.ntu.edu.tw/course/SOC_LAB/index.html/ip_design.zip