TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective.

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1 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Understanding S12X Memory Scheme May 2007 Christian Michel-Sendis RTAC – TIC Mexico CHANGE THE FUTURE

2 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 1 Agenda Introduction S12X Programming model S12X Memory resources Understanding Memory Paging: Local memory map and Paged Memory Lab 1: Accessing paged data Lab2: Linking Big Objects Global Memory map Lab 3: Working with Global Addresses -Map Option in the XEP100 Lab4: -Map Option on XEP100 Working with the XGATE Module: XINT Module XGATE Module Discussion :Understanding a template XGATE project

3 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 2 Introduction : S12X CPU – Programmer’s Model 2 - 8bit Accumulators (A & B) or 16bit Accumulator (D) Index Registers (X & Y) Stack Pointer Program Counter Condition Code Register (now 16 bits) AccD AccAAccB IX IY SP PC CCR 0 0 0 0 0 0 0 15 707

4 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 3 Introduction : S12X CPU – Programmer’s Model AccD AccAAccB IX IY SP PC CCR 0 0 0 0 0 0 0 15 707 S12X CPU’s instructions are designed to work with 16-bit addresses. The PC register for example, will only be able to point at instructions located in a 16 bit address range, from 0x0000 to 0xFFFF. This range of addresses is what can DIRECTLY be “seen” by the S12XCPU. This 16-bit addressable working space is what we call the S12X CPU’s Local Map A 16-bit addressable space corresponds to 64 Kilobytes of memory

5 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 4 Introduction : S12X CPU Local Map So, the Local Map is a 64K working space where the CPU, through the use of its instruction set, can directly read and store data and code into the on-chip memory resources On-Chip Memory resources : FLASH RAM EEPROM I/O Registers 0x0000 0xFFFF 64 Kilobytes

6 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 5 Introduction : S12X CPU Local Map How are these On-Chip Memory resources placed in the map ? FLASH RAM EEPROM I/O Registers The Local Map is split into 4 different regions Depending on the address pointed to in the local map, we will be accessing the different resources. These are the corresponding boundary addresses 0x0000 0x0800 0x1000 0x4000 0xFFFF 2K EEPROM 2K REGISTERS 12K RAM 48K FLASH

7 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 6 Introduction : S12X Memory Resources What is the problem? Let’s take a look at the memory resources available in an S12X (Figure shows an S12XEP100 device) We have > 1 MB of memory resources that we need to access! 2K Registers

8 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 7 Understanding Memory Paging. We have more memory than we can address with 16 bits! The Registers do not cause conflict because they are not bigger than 2K. EEPROM, RAM and FLASH do cause conflict because we have more available memory than space reserved for these resources in the Local Memory Map How can we access all of the available memory from the local memory map? Memory Paging for EEPROM, RAM and FLASH is used as workaround for this Local Map limitation! 0x0000 0x0800 0x1000 0x4000 0xFFFF 2K EEPROM 2K REGISTERS 12K RAM 48K FLASH

9 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 8 Understanding Memory Paging. The basic idea behind memory paging is to divide the total amount of memory into groups of bytes of fixed sizes. Each group of bytes is called a PAGE, or, a BANK * This division into pages is NOT a real physical division. It will just be seen as a division by the user’s program. A hardware mechanism will allow us to DISPLAY inside the local Map The contents of a given page. Let’s see this explained in a more graphical way : * Do not confuse Pages or Banks with memory Blocks.

10 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 9 2K EEPROM 2K REGISTERS 12K RAM 48K FLASH 0x0000 0x0800 0x1000 0x4000 0xFFFF We are going to graphically explain the idea of memory paging for the FLASH The same mechanism is used for RAM and EEPROM. Understanding Memory Paging.

11 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 10 2K EEPROM 2K REGISTERS 12K RAM 48K FLASH 0x0000 0x0800 0x1000 0x4000 0x8000 0xC000 0xFFFF 1 MB FLASH 1 - The flash is “cut” in pages of 16K 2- In the Local Map, the 48K FLASH region is subdivided in 3 - 16K regions. 3- Any 16K page from the 1MB physical array can be virtually displayed on the Local’s map middle 16K page, by writing the page number to a special register. 16K FLASH PAGE 0xFE Register PPAGE= 0xFE 16K Page PAGE 0xE0 Register PPAGE=0xE0 FLASH Paging

12 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 11 4K EEPROM 1K Page 2K EEPROM 2K REGISTERS 12K RAM 0x0000 0x0800 0x0C00 0x1000 0x4000 0x8000 0xC000 0xFFFF 1- The EEPROM is “cut” in 1K pages. 2- In the Local Map, the 2K EEPROM region is subdivided in 2- 1K regions. 3- Any 1K page from the 4K physical array can be virtually displayed on the Local’s map upper 1K page, by writing the page number to a special register. 16K FLASH FLASH PAGE WINDOW 16K FLASH Register EPAGE= 0xFC PAGE 0xFC EEPROM Paging 1K EEPROM

13 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 12 2K REGISTERS 12K RAM 0x0000 0x0800 0x0C00 0x1000 0x2000 0x4000 0x8000 0xC000 0xFFFF 16K FLASH FLASH PAGE WINDOW 16K FLASH 1K EEPROM EEPROM WINDOW 1 - The RAM is “cut” in pages of 4K 2- In the Local Map, the 12K FLASH region is subdivided in 2 regions 4K and 8K big. 3- Any 4K page from the 64K physical array can be virtually displayed on the Local’s map upper 4K page, by writing the RAM page number to a special register 64K RAM 4K Page PAGE 0xFD 8K RAM 4K RAM Register RPAGE= 0xFD RAM Paging

14 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 13 Other Memory Regions 2K REGISTERS 0x0000 0x0800 0x0C00 0x1000 0x2000 0x4000 0x8000 0xC000 0xFFFF 16K FLASH FLASH PAGE WINDOW 16K FLASH 1K EEPROM 1K EEPROM WINDOW 8K RAM 4K RAM WINDOW Q: What about the other memory regions in the local map ? A : They are mapped to FIXED locations on the physical memory arrays. The physical addresses that are mapped here are defined at chip integration. Because you do not need to handle a PAGE register to access this memory, these regions are called UNPAGED or UNBANKED

15 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 14 Paging Mechanism Paging Mechanism: We have seen how to make it work. Now let’s see what’s behind this : It’s not magic. EPAGE RPAGE PPAGE ALL Available Physical Memory Local Memory Map Memory Mapping Control Module (MMC)

16 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 15 Paging Mechanism MMC Module : It allows to convert a 16 bits address supplied by the CPU to a 23-bit address used to access the specific global (physical) memory. The additional information is supplied by the PAGE registers (RPAGE, EPAGE, PPAGE) which are 8-bits long each. CPUS12X 16 bits Address 23 bits Address MMC Global Memory EPAGE RPAGE PPAGE

17 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 16 The Global Map A 23 bit address allows to reference an address space of 2^23 = 8 MBytes! Address range is now 0x000000 – 0x7FFFFF. More addressable memory than we have available! How are our memory resources placed in this Global Map? 0x00-0000 0x7F-FFFF

18 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 17 How are our memory resources placed in this Global Map? Dedicated address areas are devoted to each memory resource. Depending on how much memory each device has, the map will be filled from the bottom-up. The areas that are left empty are said to be “unimplemented” 4MB FLASH AREA 256 Kb EEPROM AREA ~1MB RAM AREA 2.75 MB EXTERNAL SPACE AREA 2K REGISTERS 0x00_0000 0x00_0800 0x10_0000 0x14_0000 0x40_0000 0x7F-FFFF The Global Memory Map

19 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 18 How is paging reflected in the Global Memory Map? The designation of page numbers inside each available memory resource is done also from the bottom – up, starting with page number 0xFF. (Page 0xFF corresponds to the memory page with the highest addresses, for each resource) Example for the FLASH resource : 4MB FLASH AREA 256 Kb EEPROM AREA ~1MB RAM AREA EXTERNAL SPACE AREA 2K REGISTERS 0x00_0000 0x00_0800 0x10_0000 0x14_0000 0x40_0000 0x7F-FFFF 4MB FLASH AREA PAGE 0xC0 PAGE 0xFB PAGE 0xFC PAGE 0xFD PAGE 0xFE PAGE 0xFF 16K

20 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 19 Local addresses concerned by RAM WINDOW : 0x1000 – 0x1FFF All these addresses share the same upper nibble value (1) Real information is contained in the lower 3 nibbles. Values 0x000-FFF (12 bits) These 12 bits represent the OFFSET of the value inside the RAM PAGE The RPAGE Register is included with all its 8 bits It points to the relevant RAM PAGE among the 256 theoretically possible. The 3-bit FIXED value of 0-0-0 is prepended to the global address This simply fixes the position of the RAM area inside the global map. How do we translate a local address to a global address? 3-bit fixed value 0 0 0 Local RAM Window Address 12 lower bits For a local address inside the RAM window page, the following conversion is done by the MMC: GLOBAL ADDRESS [ 22 : 0] Bit 0 Bit 22 RPAGE Register 8 bits RPAGE 8 bits Bit 11 Bit 19

21 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 20 Local map (for reference) 2K REGISTERS 0x0000 0x0800 0x0BFF 0x0C00 0x1000 0x1FFF 0x2000 0x4000 0x8000 0xBFFF 0xC000 0xFFFF 16K FLASH FLASH PAGE WINDOW 16K FLASH 1K EEPROM 1K EEPROM WINDOW 8K RAM 4K RAM WINDOW EEPROM WINDOW Addresses : 0x0800-0x0BFF RAM WINDOW Addresses: 0x1000-0x1FFF FLASH WINDOW Addresses: 0x8000-0xBFFF

22 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 21 Conversion into global addresses for the FLASH and EEPROM WINDOWS An analogous conversion exists: These figures are directly taken from the Device’s datasheet, MMC chapter.

23 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 22 Unbanked Pages in the Local Map 2K REGISTERS 0x0000 0x0800 0x0C00 0x1000 0x2000 0x4000 0x8000 0xC000 0xFFFF 16K FLASH FLASH PAGE WINDOW 16K FLASH 1K EEPROM 1K EEPROM WINDOW 8K RAM 4K RAM WINDOW Let’s go back to our Local Map. Remember we have Unbanked areas? Where do these areas point to ? Specific addresses of the global memory map corresponding to these page numbers are ALWAYS visible there. RAM PAGE 0xFE RAM PAGE 0xFF FLASH PAGE 0xFD FLASH PAGE 0xFF EEPROM PAGE 0xFF

24 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 23 Paging mechanism Conclusions From this we can conclude : 1) There are memory areas that can ALWAYS be accessed in the local map without the need of playing with page registers. (unbanked areas) 2) There are memory areas that cannot be reached directly in the local map and HAVE TO be accessed by writing to page registers (banked areas) Q : Do I have to write to the Page registers every time I want to access a function or variable placed in banked memory? A: You can if you want to, or you can let the C-compiler do it for you ! OK, so, how do I make this work by using CodeWarrior ?

25 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 24 LAB1 : Using Paged RAM 1. Please Open the project called LAB1_Using_Paged_RAM 2. Make sure you have selected the “Softec HCS12” target 3. Connect your DEMO9S12XEP100 board to the USB port of your PC

26 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 25 Conclusions from LAB 1 Inside your code use the appropriate #pragma statement #pragma DATA_SEG __RPAGE_SEG segment name where segment name is a placement location that goes into paged RAM Pointers pointing to ram paged data need to be qualified with “__rptr” and will be 3 bytes big. Add the –D__FAR_DATA option to the compiler if using initialized ram variables. We introduced the notion of “logical addresses”

27 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 26 LAB2 : Allocating Big Objects 1. Please Open the project called LAB2_Allocating_Big_Objects 2. Make sure you have selected the “Softec HCS12” target 3. Connect your DEMO9S12XEP100 board to the USB port of your PC

28 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 27 Conclusions from LAB 2 Paging allows to access ALL of the memory resources, But introduces a limitation : Sizes of objects to be allocated in paged memory cannot exceed the page size. RAM paged objects limited to <4 K EEPROM paged objects limited to <1K FLASHED Paged object limited to <16K An alternative for RAM objects >4K is to use the 8K unpaged ram area in the local map. (Flash objects cannot benefit from the two 16K unpaged flash areas because these areas are not contiguous)

29 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 28 Global Addressing Lab 2 helped us to become aware of a limitation on the paging approach, especially prohibitive when attempting to allocate big objects. Many applications need to allow storing of single objects, especially single constant objects like: Large Look-up tables Bitmap images Sound How to overcome this limitation?

30 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 29 Global Addressing... Global Addressing is the answer! Global addressing allows us to access continuous ranges of 64Kbytes directly from the Global Memory map. A big 64K page window controlled by a new register, the GPAGE register, will be able to show us in a “Global View Window” a contiguous 64K space that is directly a view of the Global Memory Map. Global addressing was mainly introduced to allow the linking of objects of up to 64K.

31 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 30 4MB FLASH AREA 256 Kb EEPROM AREA ~1MB RAM AREA EXTERNAL SPACE AREA 2K REGISTERS CPU-Accessible 64K Global View Window 0x0000 0xFFFF A new register is introduced : GPAGE. The GPAGE register controls what is displayed in the Global View window. In order to “SWITCH” to global view, the CPU HAS TO use SPECIAL Global Instructions. Like so, the Local Map is not perturbed. GPAGE Register 64K Global Addressing

32 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 31 Global Addressing The upper byte of the 23-bit global address must be written to GPAGE in order to display the corresponding 64K region of the global memory map. Example : Writing 7E to GPAGE will result in the Global View Window displaying the contents of addresses 7E_0000 to 7E_FFFF. Remember that ONLY special instructions can access the Global View Window. These are called Global instructions and have the form GLDxx and GSTxx

33 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 32 HCS12X has a complete set of Load & Store instructions to allow the 7 bit global address register to form a 23 bit global address: GLDAA,GLDAB,GLDD,GLDX,GLDY,GLDS,GSTAA,GSTAB,GSTD,GSTX,GSTY, GSTS If such an instruction is executed the address is concatenated from the new 7-Bit GPAGE register + standard 16Bit address 23Bit address = {7-Bit GPAGE, 16 Bit address} Global Address GPAGE[6:0]AB[15:0] GAB[22:0]

34 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 33 Converting from Logical Addresses to Global Addresses. 4MB FLASH AREA PAGE 0xFE PAGE 0xFF 0xFC_BFFF 0xFD_8000 0xFE_BFFF 0xFF_8000 0xFF_BFFF 0x7F_FFFF 0xFD_BFFF 0xFE_8000... 0x7F_BFFF 0x7F_C000 0x7F_7FFF 0x7F_8000 0x7F_3FFF 0x7F_4000 PAGE 0xFD Logical Addresses (Banked addresses) Global Addresses PAGE 0xFC

35 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 34 LAB 3 : Using Global Addressing to Link Big Objects Please Open the project called LAB3_Using_Global_Addressing Make sure you have selected the “Softec HCS12” target Connect your DEMO9S12XEP100 board to the USB port of your PC

36 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 35 Conclusions from LAB 3 To use global addressing : 1)Edit your prm file and declare a memory area using global addresses 2)Append the character ‘G to these addresses to let the linker know they are global. 3)Remove any double declaration pertaining to this area and create a placement section for this area 4)Inside your code use the appropriate #pragma statement #pragma CONST_SEG __GPAGE_SEG segment name 5) Pointers pointing to global data need to be qualified with “__far” and will be 3 bytes in length. 6)Add the –D__FAR_DATA option to the compiler if using initialized ram variables.

37 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 36 Converting from Logical Addresses to Global Addresses. Hint : Inside the debugger you can open a small application that converts addresses. To do so: Click on Component  Open  HCS12XAdrMap Or you can directly open this application by going to : C:\Program Files\Freescale\Codewarrior for HC12 V4.6\Prog and clicking on HCS12XAdrMap.exe

38 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 37 Conclusions from LAB 3 (Continued) If global addressing has less limitations than using a banked addressing, why don’t we just always use global addressing? Global instructions have slower execution time and generate bigger code size. Global addressing is mostly intended to be used with constants or data and not with functions. Besides, will you really have a function bigger than 16K? Both Global Addressing and Banked Addressing can co-exist in the same project!

39 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 38 Pointer use and Pointer Arithmetic. Pointer definitions include a modifier to indicate the memory access approach For RPAGE memory use __rptr For EPAGE memory use __eptr For PPAGE memory use __pptr For GPAGE (global) memory use __far Once defined, pointers behave as normal for any C pointer behaviour Care must be taken when performing arithmetic on paged memory: A pointer++ operation will only Affect the lower 16 bits of the pointer. It does not affect the upper (page) byte.

40 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 39 -Map Option in the XEP100 –Map Option This option sets the memory mapping for addresses between 0x4000 and 0x7FFF for HCS12XE. This mapping is determined by the MMC control register (the ROMHM and RAMHM bits) and the compiler must be aware of the current setting to correctly perform address translations. Syntax -Map(RAM|FLASH|Exernal) ; Example -MapRAM RAM: accesses to 0x4000–0x7FFF will be mapped to 0x0F_C000-0x0F_FFFF in the global memory space (RAM area). FLASH: accesses to 0x4000–0x7FFF will be mapped to 0x7F_4000-0x7F_7FFF in the global memory space (FLASH). External: accesses to 0x4000–0x7FFF will be mapped to 0x14_4000-0x14_7FFF in the global memory space (external access).

41 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 40 -Map Option in XEP100

42 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. Working with XGATE: Basics.

43 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 42 What is XGATE? XGATE is a programmable core 16bit RISC engine Instruction set optimised for data manipulation Runs at up to 2x CPU bus speed Driven by interrupt controller Program code stored in RAM (or Flash) Accesses RAM, peripherals and Flash

44 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 43 XGATE Concept The idea of the XGATE was born out of the need to greatly improve application responsiveness and coherency through a reduction in the interrupt loading on the main CPU. Allow sequences of interrupt instructions to be executed in parallel with the normal CPU application execution. “Share the work with others”

45 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 44 Interrupt Processing Application Example CPU Running application code S12 S12X Interrupt request CPU Stalls Application code to service IRQ Interrupt complete CPU Running application code XGATE stopped CPU Running application code XGATE completely handles the IRQ CPU Running application code XGATE stopped

46 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 45 XGATE Objective Interrupts from the interrupt controller hardware can be routed to the XGATE or to the CPU. Any Interrupt routed to the XGATE will remove load from the CPU. A switch directs the interrupt signals to the CPU or to the XGATE. The XGATE can also Interrupts the CPU when the task is finished.

47 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 46 XGATE Programmer’s Model 16bit RISC architecture Rich register set R0 forced to have value 0 R1 initialised automatically by interrupt controller but can be reused R2 – R7 general purpose Full 16bit program counter Simple Condition Code Register No stack pointer Subroutine support exists in instruction set CCR (N,V,C,Z) 0 15 PC 0 15 R7 0 15 R6 0 15 R5 0 15 R4 0 15 R3 0 15 R2 0 15 R1 = Variable Base 0 15 R0=0 0 15 Event driven 16-bit RISC Engine

48 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 47 XGATE Instruction set overview Operates at 50MHz = 10ns cycle time (for XEP100) 1 cycle for all register-based instructions 2 cycles for load and store instructions 2 cycles for branches, if taken, else 1 cycle Fixed 16-bit opcode length optimised for Data movement and logic Simple fast implementation CCR (N,V,C,Z) 0 15 PC 0 15 R7 0 15 R6 0 15 R5 0 15 R4 0 15 R3 0 15 R2 0 15 R1 = Variable Base 0 15 R0=0 0 15

49 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 48 XGATE Instruction Set The instruction set is optimised for fast data handling and response to events 1..15 bit shift or rotate in one cycle Word addition/subtraction in one cycle 16-bit parity calculation in one cycle Store word to memory in two cycles Set/Clear semaphore in two cycles Bit stuffing and extraction in one cycle One cycle = 10 ns ( for the XEP100) No multiply or divide instructions CCR (N,V,C,Z) 0 15 PC 0 15 R6 0 15 R6 0 15 R5 0 15 R4 0 15 R3 0 15 R2 0 15 R1 = Base 0 15 R0=0 0 15

50 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 49 XGATE Instruction Set Traditional RISC Model : “C”-Compiler friendly Strict Load/Store Architecture All instructions involve at least one register Register addressing modes Immediate 8-Bit, 4-Bit Triadic Rd = Rs1 op Rs2 Dyadic Rd = Rd op Rs MonadicFunction(Rd) Inherent no register needed

51 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 50 Complements strengths of CPU XGATE has strengths that complement the CPU Interrupt response time  XGATE has no need to save or recover context Bit shifting and manipulation  N-bit shifts and N-bit insertion/extraction in one cycle  Bitwise parity in one cycle Runs as fast as program store will allow  Execution out of RAM as fast as 100MHz

52 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 51 XGATE – What it is not: No complex instructions like multiply, divide. Not intended to write 1,000s of lines of code. Write many small and fast handler routines.

53 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 52 XGate memory map The XGate can address 64k of memory 2k of peripheral register space 30k of FLASH 32k of RAM (Consult your device’s datasheet) XGate and CPU share access to the same physical memory This allows both processors to communicate and share tasks The S12X hardware automatically manages memory access The MCU provides an access protection system to prevent the CPU or XGate disturbing each other’s RAM contents Memory can be divided into shared, XGate write only and CPU write only regions  The size of each region is configurable 64k 2k Registers 32k RAM Flash 30k

54 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 53 XGate - Memory Space $8000 $FFFF $0000 $07FF $0800 0x00_0000 0x00_07FF 0x0F_8000 0x0F_FFFF 0x78_0800 0x78_7FFF 64k 2k Registers 32k RAM 30k Flash $7FFF 64kByte XGate Space Corresponding Global Addresses PAGE_E0 PAGE_E1 PAGE_F8 PAGE_F9 PAGE_FA PAGE_FB PAGE_FC PAGE_FD PAGE_FE PAGE_FF

55 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 54 The Interrupt Controller Module (XINT) The individual events which trigger execution of XGATE code are provided by the interrupt controller. Let’s take some minutes to see how this interrupt controller functions.

56 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 55 The Interrupt Controller Module (XINT) In a nutshell, the XINT module is responsible for : Directing interrupts to be handled by either the XGATE or the CPU. (User configurable) Determining, from all pending CPU interrupts, which is the most proprietary one that will be serviced next. (Using a Priority Level entered by the user. 7 levels of priority are accepted by the CPU) Determining, from all pending XGATE interrupts, which is the most proprietary one that will be serviced next. (Using a Priority Level entered by the user. 2 levels of priority are accepted by the XGATE An Interrupt running on XGATE can now be interrupted! (For XGATE Version 3 only) Provides movable vector table : CPU vectors can be placed in any 256 byte page

57 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 56 The Interrupt Controller Module (XINT) The CPU vector table provides us with a list of all possible interrupt sources for the application Interrupts vectors can now be relocated: By writing a value to a specific register, the Vector Base is changed. Vector Base defaults to 0xFF. Reset vectors cannot be relocated. A number, called Channel ID is used by the XGATE when an interrupt is redirected to it. each interrupt source that can be handled by XGATE has a channel ID associated. In our case, possible channel IDs are 0x1E to 0x78 = 91 interrupt sources can be redirected to XGATE. Out of reset, XINT configures all interrupts to level 1 and directs them to the CPU.

58 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 57 The Interrupt Controller Module (XINT)

59 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 58 Interrupt Selection Peripheral Modules Service Requests Interrupt Requests Interrupt Priority Decoder XGATE Module XGATE Request Priority Decoder CPU Interrupt

60 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 59 A possible system approach Peripheral Modules Interrupt Priority Decoder CPU Interrupt XGATE Module XGATE Request Priority Decoder Service Requests Interrupt Requests

61 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 60 The Interrupt Controller Module (XINT) How to redirect an interrupt to the XGATE ? Each interrupt source has a dedicated register called “Interrupt Request Configuration Data Register” When set to 1, this bit will make the XGATE handle the associated interrupt. These 3 bits contain the priority level from 0 to 7 If priority=0, interrupt is disabled.

62 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 61 Configuring the Interrupt module Each interrupt source is configured individually To save space in the memory map interrupt configuration is done switching in the relevant page of registers. One page will show 8 Interrupt configuration registers. Interrupt configuration register Choose interrupt configuration by selecting appropriate page of registers RQST| | | | |ILVL

63 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 62 Configuring interrupts How to write to the appropriate “Interrupt Request Configuration Data Register”? Another register called “Interrupt configuration address register” controls which page is shown in the local map. 1)Write the upper byte of the lower nibble of the interrupt address into this register 2)The appropriate page will be shown in the map. Write to the appropriate register inside this group of 8 registers RELAX, This is MUCH, MUCH easier to do than to explain !!!

64 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 63 Interrupt Module Example The Interrupt Processing Level is tracked in new condition code register byte on the Stack Interrupt nesting enabled by a CLI instruction inside the ISR Processing Level X X X 0 X X 3 0 X 0 X X 0 X X 0 X X X X X 0373210 Resume 3 7 interrupts 3 2 higher than pending 1 RTI 0 2 3 4 1 5 6 7 Normal Process RTI IPL[2:0] as part of the CCR-High register on Stack CCR

65 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 64 Interrupt Module Example (cont) Let’s see how to trigger a software interrupt. This will be useful in the next lab: 8 software triggers are available They can interrupt both the CPU or the XGATE They are called XGATE Software triggers because they are normally used to trigger an XGATE task.

66 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 65 Triggering a software interrupt In order to generate a software interrupt, we have to raise the corresponding xgate software trigger flag in a particular register called the XGSWT Register

67 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 66 Discussion : Understanding a template XGATE project structure in CodeWarrior OK. Let’s Get our hands dirty! 1) Please open CodeWarrior for HCS12X v4.6 2) Click on File  New Select New Project Wizard Select a name and location for your project Click next and select :  S12XEP100 as derivative  Multicore HCS12X and XGATE in RAM  C language  No PC lint  No Float Support for CPU  No Float Support for XGATE  Banked memory model  Select SofTec HCS12 connection Click on Finish

68 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. THANK YOU FOR ATTENDING!

69 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 68 EXTRA SLIDES

70 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 69 Direct Addressing Mode The direct page allows use of the more efficient direct addressing mode On S12X the direct page is not fixed at $0000 Programmable in the DIRECT register (upper 8 bits of every direct addressing mode instruction) Write once Can be placed at any 256byte boundary in memory Defaults to $0000 DIRECT DP15 DP8 64k Local Space $0000 2k Register 1k unpaged EEE 8k unpaged RAM 4k paged RAM 1k paged EEE 16k unpaged P-FLASH 16k paged P-FLASH 16k unpaged P-FLASH $1000 $4000 $8000 $C000 $FFFF

71 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 70 Direct Page handling The toolchain must be told the location of the direct page and know which variables are placed in this page for it to correctly generate the faster direct addressing mode opcodes The user must Initialise the DIRECT register (if not $0000) Define appropriate variables in the correct data segment  For CodeWarrior this is __SHORT_SEG Place the data segment at the correct address in the linker file The compiler and linker must Know the location of the DIRECT page  For CodeWarrior use the –CpDirect directive

72 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 71 Hints & Tips DIRECT Always write this even if direct page is being left at address $0000 By placing this in a paged area a larger memory size can benefit from the reduced access times  Including Global memory loads! RPAGE, EPAGE If possible, structure RAM & EEPROM use to allow the page registers to switch contexts  May benefit software that deals with different operating modes e.g. menu driven displays

73 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 72 CPU & XGATE Operation Comparison Two examples: Example 1 Scan 4 I/O ports and compare values against RAM Toggle LED every 8 times round If I/O changes then enable oscillator Example 2 Toggle one LED every 25 times round Toggle another LED every 80 times round and enable oscillator

74 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 73 Example 1 implementation Byte LoopCount,RAM_PortA,RAM_PortB,RAM_PortC; Byte RAM_PortD,RAM_PortE; // interrupt handler interrupt void APIHandler(int dummy) { Byte RAM_Changes = 0; if (PORTA != RAM_PortA) RAM_Changes |= 0x01; if (PORTB != RAM_PortB) RAM_Changes |= 0x02; if (PORTC != RAM_PortC) RAM_Changes |= 0x04; if (PORTD != RAM_PortD) RAM_Changes |= 0x08; LoopCount++; if (LoopCount%8) PORTE=PORTE^0x01; // Clear API interrupt VREGAPICL_APIF = 1; //Start up MCU if required if (RAM_Changes) PLLCTL_FSTWKP = 0; } Scan 4 I/O ports for changes Toggle LED every 8 times If I/O changes start up oscillator

75 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 74 Example 1 implementation results Code size and cycle count Source: Code compiled with CodeWarrior 4.1, results from simulator XGATE completes in 90% of CPU time

76 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 75 Example 2 implementation Byte LoopCount; // interrupt handler interrupt void APIHandler(int dummy) { LoopCount++; if (LoopCount%25) PORTE=PORTE^0x01; if (LoopCount%80) { PORTE=PORTE^0x02; //Start up MCU PLLCTL_FSTWKP = 0; } // Clear API interrupt VREGAPICL_APIF = 1; } Toggle LED every 25 times Toggle LED every 80 times Every 80 times start up oscillator

77 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 76 Example 2 implementation results Code size and cycle count Source: Code compiled with CodeWarrior 4.1, results from simulator CPU completes in 68% of XGATE time No divide instruction on XGATE

78 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 77 Guidelines for XGATE and CPU XGATE will perform best when There is arithmetic and logical operation on data in RAM There is no complex mathematics There are few peripheral accesses as a proportion of the total cycles CPU will perform best when There are mathematical operations (multiply & divide etc.) Since it is simple to program both cores in C it is very easy to compare the two and decide on the best approach

79 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 78 Suggested approaches Let’s consider some application scenarios Assume all variables are in RAM and all constants are in Flash Application 1: S12XD64, 56k code, 4k variables, 4k const  MCU has 64k Flash and 4k RAM Application 3: S12XDP512, 400k code, 20k variables, 80k const The memory configuration for each will be guided by the application requirements

80 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 79 Application 1 S12XD64, 56k code, 4k variables, 4k const In this case all of the variable space is always in the memory map so there is no need to use global or local pages For the constants there are two options Fit all the constants into unpaged Flash  Define near pointers to constants Fit all the 4k of constants in Flash into a single global page  Place all constants in a single segment in global memory  Use far pointers to access constants – Since all are in one page only one GPAGE write is needed for whole application

81 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 80 Application 2 S12XDP512, 400k code, 20k variables, 80k const In this case we must use paging for the RAM Put the 8k most commonly-accessed variables in unpaged RAM For the remaining 12k it is likely that a local RAM paging scheme will be most efficient  Maximum of three pages required 80k of constants implies two global pages If possible these should be loosely packed  This allows more control on how constants are arranged in a page  Use far pointers to access constants

82 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 81 Using local memory paging Advantages Fastest for accessing small variables Opportunity for fast context switch Multiple DIRECT addressing mode pages are possible Disadvantages Ineffective when objects are larger than a page size #pragma DATA_SEG __RPAGE_SEG PAGED_RAM unsigned char rub_far_var; #pragma DATA_SEG DEFAULT unsigned char * __rptr ptr_on_far_var;

83 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 82 Using global memory paging Advantages Large page size allows access to large objects or groups of objects with no page switching Simple to use within flash pages Disadvantages Slower than local page access since global load and store opcodes take one additional cycle #pragma DATA_SEG __GPAGE_SEG PAGED_RAM unsigned char rub_far_var; #pragma DATA_SEG DEFAULT unsigned char *__far ptr_on_far_var;

84 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 83 Accessing variables in unpaged memory #pragma DATA_SEG DEFAULT /* (near) NON-PAGED RAM */ volatile char data1_rNP = 1; /* unpaged data */ volatile char *near n_pointer1_rNP; /* 16-bit pointer in near segment */ volatile char *far f_pointer1_rNP; /* 23-bit GPAGE pointer in near segment */ volatile char *__rptr r_pointer1_rNP; /* 23-bit RPAGE pointer in near segment */ volatile char *__eptr e_pointer1_rNP; /* 23-bit EPAGE pointer in near segment */ data1_rNP = 21; 000b c615 [1] LDAB #21 000d 7b0000 [3] STAB data1_rNP n_pointer1_rNP = &data1_rNP; 0015 180300000000 [5] MOVW #data1_rNP,n_pointer1_rNP f_pointer1_rNP = &data1_rNP; 0000 ce0000 [2] LDX #GLOBAL(data1_rNP) 0003 c600 [1] LDAB #GLOBAL_PAGE(data1_rNP) 0005 7e0000 [3] STX f_pointer1_rNP:1 0008 7b0000 [3] STAB f_pointer1_rNP

85 TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2007. 84 Accessing variables in paged memory #pragma DATA_SEG RPAGE PAGED_RAM_FC /* IN PAGED RAM (PAGE FC) */ volatile char data1_rFC = 1; /* paged ram data (in page FC) */ volatile char *__rptr r_pointer1_rFC; /* 23-bit RPAGE pointer in paged ram (FC) */ volatile char *far f_pointer1_rFC; /* 23-bit GPAGE pointer in paged ram (FC) */ data1_rFC = 24; 0000 c600 [1] LDAB #PAGE(data1_rFC) 0002 5b16 [2] STAB /*RPAGE*/22 0004 c618 [1] LDAB #24 0006 7b0000 [3] STAB data1_rFC *r_pointer1_rFC = 54; 005b 8636 [1] LDAA #54 005d fd0000 [3] LDY r_pointer1_rFC:1 0060 f60000 [3] LDAB r_pointer1_rFC 0063 5b16 [2] STAB /*RPAGE*/21 0065 6a40 [2] STAA 0,Y f_pointer1_rFC = &data1_rFC; 000e ce0000 [2] LDX #GLOBAL(data1_rFC) 0011 c600 [1] LDAB #GLOBAL_PAGE(data1_rFC) 0013 7e0000 [3] STX f_pointer1_rFC:1 0016 7b0000 [3] STAB f_pointer1_rFC