存储器与可编程逻辑阵列 刘鹏 浙江大学信息与电子工程学院

Presentation on theme: "存储器与可编程逻辑阵列 刘鹏 浙江大学信息与电子工程学院"— Presentation transcript:

1 存储器与可编程逻辑阵列 刘鹏 liupeng@zju.edu.cn 浙江大学信息与电子工程学院 数字系统设计@浙大数芯
ROM, SRAM, and PLA ZDMC

2 Computer System 计算机系统 数字系统设计@浙大数芯
High-speed main memory and external auxiliary memory. Auxiliary memory operates at a much slower speed than main memory, and it stores programs and data That are not currently being used by the CPU. Memory Cell, memory word, Byte, Capacity， Density, Address, Read Operation, Write Operation, Access Time tACC, Volatile Memory, Random-Access Memory (RAM) FF registers are high-speed memory elements that are used extensively in the internal operations of a digital computer. ZDMC

3 ROM（Read Only Memory），只读存储器
ROM（Read Only Memory），只读存储器 ROM是各种存储器中结构最简单的一种。在正常工作时它存储的数据是固定不变的，只能读出，不能随时写入. 分类 固定ROM：无法更改，出厂时厂家编程 可编程ROM（PROM）：用户可写入一次 可擦可编程ROM（EPROM）：紫外线擦除 电抹可编程ROM（EEPROM）:电可擦 Technically, a ROM can be written into (programmed) only once, and this operation is normally performed at the factory. Information can only be read from the memory. All ROM is nonvolatile and will store data when electrical power is removed. ZDMC

4 电路结构框图 核心 容量概念： 地址线： 存储矩阵 容量=字×位 地址译码器 （bits） 例 EPROM 27256 地址输入
A0 A1 . An-1 0单元 1单元 2n-1单元 W0 W1 D0 D1 Db-1 数据输出 地址译码器 存储矩阵 输出缓冲器 OE 三态 控制 容量=字×位 （bits） 地址输入 例 EPROM 27256 共有15位地址，8位输出， 其容量： 注意：1k=1024 1M=1024K 1G=1024M n线---2n线译码器 二进制译码器 “位”线：数据线 “字”线：只有一个有效 ZDMC

5 CMOS-ROM 有源负载 4×2存储单元矩阵 地址译码器实现“与”功能：与阵列 存储矩阵实现 没接MOS，字线处于 高电平，D1=0
表示存储“0” 有源负载 地址译码器实现“与”功能：与阵列 A1A0=00时，W0=1，MOS导通， 字线处于低电平，D0=1。 接MOS表示存储“1” 2-4线译码器 4×2存储单元矩阵 地址码输入端 输出缓冲器 存储矩阵实现 “或”功能： “或阵” ZDMC

6 Typical timing for a ROM read operation
Typical timing for a ROM read operation 访问时间tACC is a measure of the ROM’s operating speed. Output enable time tOE, which is the delay between the CS/ input and the valid data output ZDMC

7 ROM应用 (ROM Applications)
ROM应用 (ROM Applications) 地址译码器产生2n个字线即为固定与阵列产生2n个乘积项 存储矩阵即为或阵列把乘积 项组合成m个逻辑函数输出。 输入地址信号即为电路的输入逻辑变量 Bootstrap Memory, Data Tables, Data Converter, Function Generator 另外：ROM看成查找表（LUT，Look-Up Table）系统 ZDMC

8 ROM为组合电路器件： 实现组合逻辑函数，实现时序电路中组合逻辑部分.
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9 输入变量为B3、B2、B1、B0，地址为4位；函数R3、R2、R1 、R0，输出为4个，应选用24×4的ROM
确定地址和输出 输入变量为B3、B2、B1、B0，地址为4位；函数R3、R2、R1 、R0，输出为4个，应选用24×4的ROM 存储内容（数据）： 逻辑图： 地址 数据 D3D2D1D0 0000 1 0001 2 0011 …… 15 1000 ROM 24×4 1 2 3 A 15 [0]A [1]A [2]A [3]A CS OE ZDMC

10 例. 用ROM和寄存器实现同时模10加/减可逆计数器， X=0，加法； X=1，减法。
模10计数状态需4位，所以选用4位寄存器。根据时序电路结构，可得框图： Reg CP Q 4 组合电路 Y（进位） X D 图中组合电路由ROM实现；而由寄存器作记忆电路。 ZDMC

11 存储内容（数据）： 确定地址和输出 逻辑图： 加法 计数 ROM 25×5 状态未用 REG 31 [0]A A [1]A [2]A
输入变量为Q3、Q2、Q1、Q0和X，地址为5位； 输出D3、D2、D1 、D0和Y ，5个，应选用25×5的ROM 地址 数据 00000 00001 00010 …… 01000 01001 10000 10~15 11001 10001 11000 00111 26~31 加法 计数 逻辑图： ROM 25×5 1 2 3 4 A 31 [0]A [1]A [2]A [3]A [4]A CS OE CP REG X 状态未用 减法 计数 状态未用 ZDMC

12 例：用ROM设计一个组合电路，该电路输入是3位二进制数，输出是输入数值的平方。
列出组合电路的真值表。一般情况下真值表中所有可能的输入和输出都要列出。 三个输入端对应8个字，每个字4位，因此ROM的容量是8x4。 ROM真值表 A2 A1 A0 B5 B4 B3 B2 1 8x4ROM A0 A1 A2 B0 B1 B2 B3 B4 B5 ZDMC

13 电路真值表 输出B0等于输入A0,输出B1一直为0. 本例中有三个输入端和四个输出端。 输入 输出 A2 A1 A0 B5 B4 B3 B2
十进制 1 4 9 16 25 36 49 输出B0等于输入A0,输出B1一直为0. 本例中有三个输入端和四个输出端。 ZDMC

14 SARM General Memory Operation (Static Random-Access Memory)
SARM General Memory Operation (Static Random-Access Memory) Diagram of a 32 x 4 memory; Virtual arrangement of memory cells into 32 four-bit words. ZDMC

15 Typical SRAM Organization: 16-word x 4-bit
Typical SRAM Organization: 16-word x 4-bit Din 3 Din 2 Din 1 Din 0 WrEn - + Wr Driver - + Wr Driver - + Wr Driver - + Wr Driver Word 0 A0 SRAM Cell SRAM Cell SRAM Cell SRAM Cell A1 Word 1 Address Decoder A2 SRAM Cell SRAM Cell SRAM Cell SRAM Cell A3 : : : : This picture shows you how to connect the SRAM cells into a 15-word by 4-bit SRAM array. The word lines are connected horizontally to the address decoder while the bit lines are connected vertically to the sense amplifier and write driver. **** What do you think is longer? Word line or bit line **** Since a typical SRAM will have thousands if not millions of words (vertical) and usually be less than 10s of bits, the bit line will be much much much longer than the word line. This is bad because if we have a large load on the word line (large capacitance), we can always build a bigger address decoder to drive them no sweat. But for the bit lines, we still have to rely on the tiny transistors (SRAM cell). That’s why we need to precharge them to high and use sense amp to detect the differences. Read enable is not needed here because if Write Enable is not asserted, read is by default.(Don’t need Read Enable) The internal logic will detect an address changes and precharge the bit lines. Once the bit lines are precharged, the values of the new address will appear at the Dout pin. +2 = 32 min. (Y:12) Word 15 SRAM Cell SRAM Cell SRAM Cell SRAM Cell - + Sense Amp - + Sense Amp - + Sense Amp - + Sense Amp Dout 3 Dout 2 Dout 1 Dout 0 ZDMC

16 Static RAM Cell (静态随机访问存储器单元) Random-Access Memory
Static RAM Cell (静态随机访问存储器单元) Random-Access Memory 6-Transistor SRAM Cell word (row select) 1 1 Read operation: 1. Select row 2. Cell pulls one line low and one high 3. Sense output on bit and bit Write operation: 1. Drive bit lines (e.g, bit=1, bit=0) 2. Select row Why does this work? When one bit-line is low, it will force output high; that will set new state bit bit The classical SRAM cell looks like this. It consists of two back-to-back inverters that serves as a flip-flop. Here is an expanded view of this cell, you can see it consists of 6 transistors. In order to write a value into this cell, you need to drive from both sides. For example, if you want to write a 1, you will drive “bit” to 1 while at the same time, drive “bit bar” to zero. Once the bit lines are driven to their desired values, you will turn on these two transistors by setting the word line to high so the values on the bit lines will be written into the cell. Remember now these are very very tiny transistors so we cannot rely on them to drive these long bit lines effectively during read. Also, the pull down devices are usually much stronger than the pull up devices. So the first thing we need to do on read is to charge these two bit lines to a high values. Once these bit lines are charged to high, we will turn on these two transistors so one of these inverters (the lower one in our example) will start pulling one of the bit line low while the other bit line will remain at HI. It will take this small inverter a long time to drive this long bit line to low but we don’t have to wait that long since all we need to detect the difference between these two bit lines. And if you ask any circuit designer, they will tell you it is much easier to detect a “differential signal” (point to bit and bit bar) than to detect an absolute signal. +2 = 30 min. (Y:10) ZDMC

17 Logic Diagram of a Typical SRAM
Logic Diagram of a Typical SRAM A D OE_L 2 N “words” x M bit SRAM M WE_L Write Enable is usually active low (WE_L) Din and Dout are combined to save pins: A new control signal, Output Enable (OE_L) WE_L is asserted (Low), OE_L is unasserted (High) D serves as the data input pin WE_L is unasserted (High), OE_L is asserted (Low) D is the data output pin Neither WE_L and OE_L are asserted? Chip is disconneted Never both asserted! Here is the logic diagram of a typical SRAM. In order to save pins, Din and Dout are combined into a set of bidirectional pins so you need a new control signal: Output Enable. Both write enable and output enable are usually asserted low. When Write Enable is asserted, the D pins serve as the data input pin. When Output Enable is asserted, the D pins serve as the data output pin. +1 = 33 min. (Y:13) or chipSelect (CS) + WE ZDMC

18 Typical SRAM Timing OE determines direction Hi = Write, Lo = Read Writes are dangerous! Be careful! Double signaling: OE Hi, WE Lo A D OE_L 2 N words x M bit SRAM M WE_L Write Timing: Read Timing: Write Setup Time Write Hold Time High Z D Data In Data Out Data Out Read Access Time Read Access Time Junk A Write Address Read Address Read Address For write, you set up your address and data on the A and D pins and then you generate a write pulse that is long enough for the write access time. For simplicity, I have assumed the Write setup time for address and data to be the same. In real life, they can be different. For read operation, you have disasserted Wr Enable and assert Output Enable. Since you are supplying garbage address here so as soon as you assert OE_L, you will get garbage out. If you then present an valid address to the SRAM, valid data will be available at the output after a delay of the Write Access Time. SRAM’s timing is much simpler than the DRAM timing which I will show you later. +1 = 34 min. (Y:14) OE_L WE_L ZDMC

19 Programmable Logic Arrays (PLAs)
Programmable Logic Arrays (PLAs) Pre-fabricated building block of many AND/OR gates Actually NOR or NAND ”Personalized" by making or breaking connections among gates Programmable array block diagram for sum of products form • • • inputs AND array • • • outputs OR array product terms ZDMC

20 Enabling Concept Shared product terms among outputs F0 = A + B' C'
Enabling Concept Shared product terms among outputs F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A example: input side: personality matrix 1 = uncomplemented in term 0 = complemented in term – = does not participate product inputs outputs term A B C F0 F1 F2 F3 AB 1 1 – B'C – AC' 1 – B'C' – A 1 – – output side: reuse of terms 1 = term connected to output 0 = no connection to output ZDMC

21 Before Programming All possible connections available before "programming" In reality, all AND and OR gates are NANDs ZDMC

22 Simplified PLD Symbology
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23 After Programming Unwanted connections are "blown"
After Programming Unwanted connections are "blown" Fuse (normally connected, break unwanted ones) Anti-fuse (normally disconnected, make wanted connections) A B C F1 F2 F3 F0 AB B'C AC' B'C' ZDMC

24 Alternate Representation for High Fan-in Structures
Alternate Representation for High Fan-in Structures Short-hand notation--don't have to draw all the wires Signifies a connection is present and perpendicular signal is an input to gate notation for implementing F0 = A B + A' B' F1 = C D' + C' D A B C D AB AB+A'B' A'B' CD' CD'+C'D C'D ZDMC

25 Programmable Logic Array Example
Programmable Logic Array Example Multiple functions of A, B, C F1 = A B C F2 = A + B + C F3 = A' B' C' F4 = A' + B' + C' F5 = A xor B xor C F6 = (A xnor B xnor C)’ full decoder as for memory address bits stored in memory A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC A B C F1 F2 F3 F4 F5 F6 A B C F1 F2 F3 F4 F5 F6 ZDMC

26 PLA Design Example BCD to Gray code converter
PLA Design Example BCD to Gray code converter A B C D W X Y Z – – – – – 1 1 – – – – – – X 1 X X X X X D A B C X 0 X X X X X D A B C K-map for W K-map for X X 0 X X X X X D A B C X 1 X X X X X D A B C minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' K-map for Y K-map for Z ZDMC

27 PLA Design Example (cont’d)
PLA Design Example (cont’d) Code converter: programmed PLA A B C D W X Y Z A BD BC BC' B C A'B'C'D BCD AD' BCD' minimized functions: W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' not a particularly good candidate for PLA implementation since no terms are shared among outputs however, much more compact and regular implementation when compared with discrete AND and OR gates ZDMC

28 PLA Design Example BCD to Gray code converter
PLA Design Example BCD to Gray code converter A B C D W X Y Z – – – – – 1 1 – – – – – – A A X 1 X X X X X X 0 X X X X X D D C C B B K-map for W K-map for X A A X 0 X X X X X X 1 X X X X X minimized functions: W = X = Y = Z = D D C C B B K-map for Y K-map for Z ZDMC

29 PLA Design Example #1 BCD to Gray code converter BC’
PLA Design Example #1 BCD to Gray code converter A B C D W X Y Z – – – – – 1 1 – – – – – – A A X 1 X X X X X X 0 X X X X X D D C C B B K-map for W K-map for X BC’ A A X 0 X X X X X X 1 X X X X X minimized functions: W = X = Y = Z = D D C C B B K-map for Y K-map for Z ZDMC

30 Multiplexer / Demultiplexer: Making Connections
Multiplexer / Demultiplexer: Making Connections Direct point-to-point connections between gates Multiplexer: route one of many inputs to a single output Demultiplexer: route single input to one of many outputs control control multiplexer demultiplexer 4x4 switch ZDMC

31 Multiplexers/Selectors
Multiplexers/Selectors Multiplexers/Selectors: general concept 2n data inputs, n control inputs (called "selects"), 1 output Used to connect 2n points to a single point Control signal pattern forms binary index of input connected to output I1 I0 A Z A Z 0 I0 1 I1 Z = A' I0 + A I1 functional form logical form two alternative forms for a 2:1 Mux truth table ZDMC

32 Multiplexers/Selectors (cont'd)
Multiplexers/Selectors (cont'd) 2:1 mux: Z = A' I0 + A I1 4:1 mux: Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7 In general, Z =  (mkIk) in minterm shorthand form for a 2n:1 Mux n 2 -1 k=0 I0 I1 I2 I3 I4 I5 I6 I7 A B C 8:1 mux Z I0 I1 I2 I3 A B 4:1 mux Z I0 I1 A 2:1 mux Z ZDMC

33 Cascading Multiplexers
Cascading Multiplexers Large multiplexers implemented by cascading smaller ones Z I0 I1 I2 I3 A I4 I5 I6 I7 B C 4:1 mux 2:1 mux 8:1 mux alternative implementation C Z A B 4:1 mux 2:1 mux I4 I5 I2 I3 I0 I1 I6 I7 8:1 mux control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7 control signal A chooses which of the upper or lower mux's output to gate to Z ZDMC

34 Multiplexers as Lookup Tables (LUTs)
Multiplexers as Lookup Tables (LUTs) 2n:1 multiplexer implements any function of n variables With the variables used as control inputs and Data inputs tied to 0 or 1 In essence, a lookup table Example: F(A,B,C) = m0 + m2 + m6 + m = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1) C A B S2 8:1 MUX S1 S0 F ZDMC

35 Multiplexers as LUTs (cont’d)
Multiplexers as LUTs (cont’d) 2n-1:1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement Example: F(A,B,C) = m0 + m2 + m6 + m = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1) C A B S2 8:1 MUX S1 S0 A B C F C' C' A B S1 S0 F 4:1 MUX C' C' 0 1 F ZDMC

36 Multiplexers as LUTs (cont’d)
Multiplexers as LUTs (cont’d) Generalization Example: F(A,B,C,D) implemented by an 8:1 MUX I0 I In-1 In F In In' 1 four possible configurations of truth table rows can be expressed as a function of In n-1 mux control variables single mux data variable C A B 1 D D’ D D’ D’ S2 8:1 MUX S1 S0 1 0 1 1 0 0 D A 0 1 B C choose A,B,C as control variables multiplexer implementation ZDMC

37 Demultiplexers / Decoders
Demultiplexers / Decoders Decoders / demultiplexers: general concept Single data input, n control inputs, 2n outputs Control inputs (called “selects” (S)) represent binary index of output to which the input is connected Data input usually called “enable” (G) 1:2 Decoder: O0 = G  S’ O1 = G  S 3:8 Decoder: O0 = G  S2’  S1’  S0’ O1 = G  S2’  S1’  S0 O2 = G  S2’  S1  S0’ O3 = G  S2’  S1  S0 O4 = G  S2  S1’  S0’ O5 = G  S2  S1’  S0 O6 = G  S2  S1  S0’ O7 = G  S2  S1  S0 2:4 Decoder: O0 = G  S1’  S0’ O1 = G  S1’  S0 O2 = G  S1  S0’ O3 = G  S1  S0 ZDMC

38 Demultiplexers as General-Purpose Logic
Demultiplexers as General-Purpose Logic n:2n decoder implements any function of n variables With the variables used as control inputs Enable inputs tied to 1 and Appropriate min-terms summed to form the function A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC C A B S2 3:8 DEC S1 S0 “1” demultiplexer generates appropriate Min-term based on control signals (it "decodes" control signals) ZDMC

39 Demultiplexers as General-Purpose Logic (cont’d)
Demultiplexers as General-Purpose Logic (cont’d) F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D’ + A B C F3 = (A' + B' + C' + D') A B 0 A'B'C'D' 1 A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD' 7 A'BCD 8 AB'C'D' 9 AB'C'D 10 AB'CD' 11 AB'CD 12 ABC'D' 13 ABC'D 14 ABCD' 15 ABCD 4:16 DEC Enable C D F1 F2 F3 ZDMC

40 Cascading Decoders 5:32 decoder 1x2:4 decoder 4x3:8 decoders
Cascading Decoders 5:32 decoder 1x2:4 decoder 4x3:8 decoders 0 A'B'C'D'E' A'BC'DE' 3:8 DEC 3:8 DEC S2 S1 S0 S2 S1 S0 F 2:4 DEC S1 S0 ABCDE 0 AB'C'D'E' AB'CDE A B 3:8 DEC 3:8 DEC S2 S1 S0 S2 S1 S0 C D E C D E ZDMC

41 Read-only Memories Two dimensional array of 1s and 0s
Read-only Memories Two dimensional array of 1s and 0s Entry (row) is called a "word" Width of row = word-size Index is called an "address" Address is input Selected word is output word lines (only one is active – decoder is just right for this) 1 1 1 1 n 2 -1 i word[i] = word[j] = 1010 decoder j internal organization 0 n-1 Address bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) ZDMC

42 ROMs and Combinational Logic
ROMs and Combinational Logic Combinational logic implementation (two-level canonical form) using a ROM F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C' truth table A B C F0 F1 F2 F3 block diagram ROM 8 words x 4 bits/word address outputs A B C F0 F1 F2 F3 ZDMC

43 memory array (2n words by m bits)
ROM Structure Similar to a PLA structure but with a fully decoded AND array Completely flexible OR array (unlike PAL) n address lines • • • inputs decoder • • • outputs memory array (2n words by m bits) m data lines 2n word lines ZDMC

44 ROM vs. PLA ROM Design time is short (no need to minimize output functions) Most input combinations are needed (e.g., code converters) Little sharing of product terms among output functions Size doubles for each additional input Can't exploit don't cares Cheap (high-volume component) Can implement any function of n inputs Medium speed PLA Design tools are available for multi-output minimization There are relatively few unique min-term combinations Many min-terms are shared among the output functions Most complex in design, need more sophisticated tools Can implement any function up to a product term limit Slow (two programmable planes) ZDMC

45 Expanding Word Size and Capacity
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46 A system with incomplete address decoding
A system with incomplete address decoding In many instances, it is necessary to use various memory devices in the same memory system. The ROM portion is made up of two 8K x 8 devices (PROM-0 and PROM-1). The RAM section requires a single 8K x 8 device. The EEPROM available is only a 2K x 8 device. The memory system requires a decoder to select only one device at a time. This decoder divides the entire memory space (assuming 16 address bits) into 8K address blocks. The upper three address lines control the decoder. The 13 lower-order address lines are tied directly to the address inputs on the memory chips. The only exception to this the EEPROM, which has only 11 address lines for its 2-Kbyte capacity. The same contents of the EEPROM will also appear at the addresses FFF, FF, and FFF. ZDMC