(Combinational Circuit)

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(Combinational Circuit)

A B C S 1 組合邏輯應用電路-半加器 半加器(Half-Adder:HA) 被加數A，加數B，進位C，和S 的真值表 半 S A
-輸入：被加數、加數 -輸出:和(Sum) 、進位(Carry out) 被加數A，加數B，進位C，和S 的真值表 被加數 加數 進位 A B C S 1 A B S C

被加數A，加數B，進位輸入Ci，和S，進位輸出Ci+1 的真值表

-多位元的加法器，須將「半加器」或「全加器」以串接方式連接，最左邊為最高位元(MSB)，最右邊為最低位元(LSB) Ci Ci+1 C Ci Ci+1

TTL 4位元（4－bit）的全加器: 7483(GND:第12腳,Vcc:第5腳)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity fulladd is port ( cin : in integer range 0 to 1; A, B : in integer range 0 to 128; sum : out integer range 0 to 256); end fulladd; architecture fulladd_logic of fulladd is begin sum <= A + B + cin; end fulladd_logic;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; use ieee.std_logic_arith.all; Entity ADDER_16 is port ( A,B :in std_logic_vector(15 downto 0); S :out std_logic_vector(15 downto 0)); End ADDER_16 architecture ADDER_16_logic of ADDER_16 is begin S <= A+B; end ADDER_16_logic ;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity BCD_adder is port (A, B :in std_logic_vector(3 downto 0); Y : out std_logic_vector(4 downto 0)); end BCD_adder; architecture BCD_adder_logic of BCD_adder is signal Z : std_logic_vector(4 downto 0); signal adjust : std_logic; begin Z <= (‘0” & A) + B; adjust <=‘1’ when z>9 else ‘0’; Y<= Z when (adjust=‘0’) else Z+6; end BCD_adder_logic;

-輸入:被減數(A)、減數(B) 、 前一級借位輸入(N)

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ADD_SUB is port ( A, B :in bit_vector(3 downto 0); select :in boolean; RESULT : bit_vector(4 downto 0)); end ADD_SUB; architecture ADD_SUB_logic of ADD_SUB is begin process (select, A , B) if select=‘0’ then RESULT <=A+B; else RESULT <= A-B; end if; end process end ADD_SUB_logic;

比較器:兩個輸入大小比較，輸出的結果有三種： (1)A＞B (2)A＝B (3)A＜B 一位元比較器，真值表如下:

(高位元大於) (高位元相等且低位元大於) (高位元相等且低位元相等) (高位元小於) (高位元相等且低位元小於)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity comparator_8 is port ( A,B :in std_logic_vector(7 downto 0); Large, Equal, Small :out std_logic)); end comparator_8; architecture comparator_8_logic of comparator_8 is begin Large <=‘1’ when A>B else ‘0’; Equal <=‘1’ when A=B else ‘0’; Small <=‘1’ when A<B else ‘0’; end comparator_8_logic;

多工器:將多條輸入線訊號，選擇其中一條連接至「單一輸出線」。多工器的輸入線(一般均為2n條)，由一組「選擇線(n條)」來決定。

S1 S0

library ieee; use ieee.std_logic_1164.all; entity mux8to1 is port ( X :in std_logic_vector(2 downto 0); D0,D1,D2,D3,D4,D5,D6,D7: in std_logic; Y :out std_logic); end mux8to1; architecture mux8to1 _logic of mux8to1 is begin Y <= D0 when X=“000” else D1 when X=“001” else D2 when X=“010” else D3 when X=“011” else D4 when X=“100” else D5 when X=“101” else D6 when X=“110” else D7 ; end mux8to1 _logic;

library ieee; use ieee.std_logic_1164.all; entity mux4to1_8 is port ( X :in std_logic_vector(1 downto 0); D0,D1,D2,D3 : in std_logic_vector(7 downto 0); Y :out std_logic_vector(7 downto 0)); end mux4to1_8; architecture mux4to1_8 _logic of mux4to1_8 is begin Y <= D0 when X=“00” else D1 when X=“01” else D2 when X=“10” else D3 ; end mux4to1 _logic ;

S1 S0 Y0 Y1 Y2 Y3 X 1 S0 Y0 Y1 X 1

library ieee; use ieee.std_logic_1164.all; entity demux1to4 is port ( X :in std_logic_vector(2 downto 0); data :in std_logic D0,D1,D2,D3: out std_logic); end demux1to4; architecture demux1to4_logic of demux1to4 is begin D0 <= data when X=“00” else ‘0’; D1 <= data when X=“01” else ‘0’; D2 <= data when X=“10” else ‘0’; D3 <= data when X=“11” else ‘0’; end demux1to4_logic;

編碼器 將輸入訊號中的一個訊號(每次只能有1條輸入線動作)轉換成被編碼 的輸出訊號 編碼器具有M條輸入線及N條輸出線(其中M≦2N)，稱為「M×N編碼器」  例: 4×2編碼器 -將4個輸入線分別轉換成二進碼輸出 -真值表如下

 8×3編碼器

library ieee; use ieee.std_logic_1164.all; entity encode8to3 is port ( D0,D1,D2,D3,D4,D5,D6,D7: in std_logic; Y2,Y1,Y0 :out std_logic); end encode8to3; architecture encode8to3_logic of encode8to3 is begin Y2 <= D4 or D5 or D6 or D7; Y1 <= D2 or D3 or D6 or D7; Y0 <= D1 or D3 or D5 or D7; end encode8to3_logic;

library ieee; use ieee.std_logic_1164.all; entity encode8to3 is port ( X : in std_logic_vector(7 downto 0); Y : out std_logic_vector(2 downto 0)); end encode8to3; architecture encode8to3_logic of encode8to3 is begin with X select Y <= “000” when “ ”, “001” when “ ”, “010” when “ ”, “011” when “ ”, “100” when “ ”, “101” when “ ”, “110” when “ ”, “111” when “ ”, “000” when others, end encode8to3_logic;

 BCD編碼器

 :「BCD優先編碼器」 74148 : 8×3優先編碼器

library ieee; use ieee.std_logic_1164.all; entity encoder74147 is port ( D :in std_logic_vector(9 downto1); Y :out std_logic_vector(3 downto 0)); end encoder74147; architecture encoder74147_logic of encoder74147 is begin Y <= “0110” when D(9)=‘0’ else “0111” when D(8)=‘0’ else “1000” when D(7)=‘0’ else “1001” when D(6)=‘0’ else “1010” when D(5)=‘0’ else “1011” when D(4)=‘0’ else “1100” when D(3)=‘0’ else “1101” when D(2)=‘0’ else “1110” when D(1)=‘0’ else “1111”; end encoder74147_logic;

(a) 用74148 設計 16×4優先編碼器。 (b)當「10」、「5」的訊號驅動時，說明電路的動作。

解碼器: -功能與編碼器相反 -具有M個輸入訊號而有N個輸出訊號( N≦2M)，稱為「M×N解碼器」 -將輸入的碼轉換成另一種碼輸出，可稱為「碼轉換器」 2x4解碼器 A B Y3 Y2 Y1 Y0 1 3x8解碼器

BCD 解碼器

library ieee; use ieee.std_logic_1164.all; entity encoder_BCD is port ( X :in std_logic_vector(3 downto1); Y :out std_logic_vector(9 downto 0)); end encoder_BCD; architecture encoder_BCD_logic of encoder_BCD is begin Y(0) <= ‘1’ when X=‘0000’ else ‘0’; Y(1) <= ‘1’ when X=‘0001’ else ‘0’; Y(2) <= ‘1’ when X=‘0010’ else ‘0’; Y(3) <= ‘1’ when X=‘0011’ else ‘0’; Y(4) <= ‘1’ when X=‘0100’ else ‘0’; Y(5) <= ‘1’ when X=‘0101’ else ‘0’; Y(6) <= ‘1’ when X=‘0110’ else ‘0’; Y(7) <= ‘1’ when X=‘0111’ else ‘0’; Y(8) <= ‘1’ when X=‘1000’ else ‘0’; Y(9) <= ‘1’ when X=‘1001’ else ‘0’; end encoder_BCD_logic;

7442（BCD解碼器） 74138（3×8解碼器） 74139（2×4解碼器）

利用7442設計一個3×8的解碼器 D=0, 3x8 解碼器,Y0~Y7有一個輸出為0 D=1, Y0~Y7 輸出全為”1”

利用7442設計一個4×16的解碼器 當D=0時 -7442-A致能(ON) -7442-B禁能(OFF) - 解碼輸出為Y0～Y7 當D=1時 A禁能(OFF) -7442-B致能(ON) -解碼輸出為Y8～Y15

七段顯示器 -將7個長條形的發光二極體LED排列，可顯示數字0～9(圖A) -類型:共陽型(common-anode)(圖B),共陰型(common-cathode)(圖C): 圖B 圖C 圖A

@7447,74247:「共陽型」七段顯示器解碼器 @7448,74248:「共陰型」七段顯示器解碼器  D、C、B、A輸入腳：D為高位元，A為低位元  a、b、c、d、e、f、g 輸出腳 -連接至七段顯示器LED輸入端,可串接200Ω～300Ω限流電阻避免 LED燒毀  LT（Lamp Test) 燈管測試腳：輸入「低電位」可測試七段顯示器LED好壞  Ripple Blanking Input(RBI腳)：控制是否顯示“0”字形 -輸入「低電位」時且DCBA為「0000」時，不顯示“0”當DCBA不為「0000」時，顯示正常 -若輸入為「高電位」則正常顯示。  Blanking Input/Ripple Blanking Output (BI/RBO腳) -為「輸入腳」時，若輸入「低電位」，七段顯示器LED均不亮 -為「輸出腳」時，若輸入腳DCBA=0000且RBI=「0」時，BI/RBO=0,可串接至另一級七段 顯示器RBI，控制不顯示“0”。

library ieee; use ieee.std_logic_1164.all; entity encoder_7seg is port ( X : in std_logic_vector(3 downto1); Y : out std_logic_vector(9 downto 0); comm : out std_logic ); end encoder_7seg; architecture encoder_7seg _logic of encoder_7seg is begin comm <=‘1’; with X select Y <= “ ” when “0000”, Y <= “ ” when “0001”, Y <= “ ” when “0010”, Y <= “ ” when “0011”, Y <= “ ” when “0100”, Y <= “ ” when “0101”, Y <= “ ” when “0110”, Y <= “ ” when “0111”, Y <= “ ” when “1000”, Y <= “ ” when “1001”, Y <= “ ” when “1010”, Y <= “ ” when “1011”, Y <= “ ” when “1100”, Y <= “ ” when “1101”, Y <= “ ” when “1110”, Y <= “ ” when “1111”; Y <= “ ” when others; end encoder_7seg_logic;