数字系统设计 Digital System Design

数字系统设计 Digital System Design
EE141 数字系统设计 Digital System Design -----验证与测试王维东 Weidong Wang 浙江大学信息与电子工程学院 College of Information Science & Electronic Engineering 信息与通信工程研究所 Zhejiang University Spring – Lec. #10

任课教师王维东 TA: 浙江大学信息与电子工程学院, 信电楼306 邮箱：wdwang@zju.edu.cn
EE141 任课教师王维东浙江大学信息与电子工程学院, 信电楼306 College of Information Science & Electronic Engineering Zhejiang University, Hangzhou, Tel: (O) Mobile: TA: 陈佳云 Jiayun CHEN， ; 陈彬彬 Binbin CHEN, ; Office Hours：玉泉信电楼 308室（可以微信或邮件联系）. Spring – Lec. #10

Prerequisites预修课程电子电路基础电子线路 C语言 How to learn this Course?
Not only listening, thinking and waiting …. But Exercise, Simulation, Practice!

课程简介课程代码：111C0120 参考书阎石, 数字电子技术基础, 第6版, 高等教育出版社, 2016.
EE141 课程简介课程代码：111C0120 参考书阎石, 数字电子技术基础, 第6版, 高等教育出版社, 2016. 王金明著，数字系统设计与Verilog HDL，电子工业出版社，第6版补充讲义/期中考试前预备 Stanford 大学 108A课程notes. R.H.Katz, G.Borriello, Contemporary Logic Design, second edition,电子工业出版社, 2005. M.M.Mano, 数字设计(第四版), 电子工业出版社, 2010. Spring – Lec. #10

Other Course Info Website: http://mypage.zju.edu.cn/wdwd/教学工作/
学在浙里: 数字系统设计2018 Check frequently 答疑玉泉信电楼308室/周三周五下午2:30-5:00 上课课间、课后均可，微信群/数字系统设计，短信均可

Grading (考核) Final grades will be computed approximately as follows:
平时（含课程作业、期中考试+小测验、Project、出勤等）30% Class Room Check Homework Sets 作业每周三上交截止期为课后一周内有效 Project 2 projects (1 or 2 members team) Project-2可选（总评加分1~5分，但不超过平时成绩范围） Finial Exam期末闭卷考试 - 70% 上课说明此门课程的成绩合成：平时成绩包括平时小测验、期中考试、作业、出勤、课堂讨论、论文

授课时间和地点： 2018年春夏学期，地点：紫金港西2-309(多)
周三上午，第1、2节(8:00-9:35) 星期五上午，第1、2节(8:00-9:35) 地点：紫金港西2-309(多) 学在浙里/数字系统设计2018

课程结构数字理论知识(必备) 数字电路分析与设计脉冲电路与接口控制器与数字系统微处理器简介与设计数字系统和编码、逻辑代数、门电路
EE141 课程结构数字理论知识(必备) 数字系统和编码、逻辑代数、门电路数字电路分析与设计组合逻辑电路触发器、半导体存贮器、可编程器件时序逻辑电路脉冲电路与接口控制器与数字系统状态机控制器微码控制器测试和验证微处理器简介与设计指令集 4位CPU Spring – Lec. #10

讲义第九章验证与测试

9.1 引言系统可测性设计（design for testability，DFT） DFT策略 DFT是整个设计过程一个非常重要的组成部分
在设计流程中需要尽早考虑如果你不测试它，系统很可能不工作 DFT策略提供必要的电路以使测试过程快速且全面提供测试激励矢量测试过程需要的降低成本希望测试序列尽可能短但仍能覆盖大部分可能存在的缺陷。

9.2 生产测试过程诊断测试功能测试参数测试芯片和板级调试期间识别和指出失效的部位对于给定的失效部件
确定一个制造出的元件是否能工作。每一个制造出来的芯片都要经过这一测试直接的影响芯片成本测试尽可能简单快速参数测试在各种工作条件（如温度和电源电压）下检查许多非离散参数，如噪声容限、传播延时和最大时钟频率参数测试一般分为静态和动态测试。

9.2.生产测试过程 Introduction Production test Design for test.
The fabrication process is one of the most precise manufacturing methods we know of, but it is still not perfect. Each time a chip is made, there is a finite chance that at least one of the millions of transistors or wires will have an error in it. Production test Since users of the chips assume that the chip is function, we need to have some method to sort out the function chips from the bad ones. a critical part of manufacturin Design for test. Given the complexity of today’s chips, designers need to add features to the chip to make production testing possible.

Design Methodology in Detail
Design Specification Postsynthesis Design Validation Design Partition Postsynthesis Timing Verification Design Entry Behavioral Modeling Test Generation and Fault Simulation Simulation/Functional Verification Cell Placement/Scan Insertation/Routing Design Integration And Verification Verify Physical and Electrical Rules Pre-Synthesis Sign-Off Synthesize and Map Gate-level Net List Design Sign-Off Synthesize and Map Gate-level Net List

一个典型的生产测试

自动测试仪

9.3.可测性设计 Testing of Logic Circuits 在设计过程的早期考虑测试 Fault Models故障模型
EE141 9.3.可测性设计 Testing of Logic Circuits Fault Models故障模型 Test Generation and Coverage Fault Detection Design for Test 在设计过程的早期考虑测试可能简化整个验证过程所有可能的输入矢量并观察相应的响应实现验证该电路的正确性

Fault Model故障模型 Stuck-At固定故障Model
Assume selected wires (gate input or output) are “stuck at”固定logic value 0 or 1故障 Models curtain kinds of fabrication flaws that short circuit wires to ground or power, or broken wires that are floating Wire w stuck-at-0: w/0 Wire w stuck-at-1: w/1 Often assume there is only one fault at a time—even though in real circuits multiple simultaneous faults are possible and can mask each other Obviously a very simplistic model!

Fault Model Simple example: w1 a/1 f w2 b see 1 w3 c but should be 0
Generate a testcase to determine if a is stuck at 1 Try 000 If a stuck at 1, expect to see f = 0, but see 1 instead w1 w2 w3 see 1 but should be 0 a/1 b c f d

Fault Model Simple example w1 w2 w3 a b c d f Test Set Test w1 w2 w3
000 001 010 011 100 101 110 111 a/0 X X X a/1 b/0 X b/1 c/0 c/1 d/0 d/1 X X f/0 X X X X X f/1 Fault Detected Test Set

Problems with Fault Model故障模型
In general, n-input circuits require much less than 2n test inputs to cover all possible stuck-at-faults in the circuit However, this number is usually still too large in real circuits for practical purposes Finding minimum test cover is an NP-hard problem too（NP难题，non-deterministic polynomial缩写）

Path Sensitization Wire-at-time testing too laborious
Better to focus on wiring paths, enabling multi-wire testing at the same time “Activate” a path so that changes in signal propagating along the path affects the output

Path Sensitization Simple Example: a w1 b w2 1 c w3 f w4 1
f w4 To activate the path, set inputs so that w1 can influence f E.g., w2 = 1, w3 = 0, w4 = 1 AND gates: one input at 1 passes the other input NOR gates: one input at 0 inverts the other input To test: w1 set to 1 should generate f = 0 if path ok faults a/0, b/0, c/1 cause f = 1 w1 set to 0 should generate f = 1 if path ok faults a/1, b/1, c/0 cause f = 0 One test can capture several faults at once! 1

Path Sensitization Good news: one test checks for several faults
Number of paths much smaller than number of wires Still an impractically large number of paths for large-scale circuits Path idea can be used to “propagate” a fault to the output to observe the fault Set inputs and intermediate values so as to pass an internal wire to the output while setting inputs to drive that internal wire to a known value If propagated value isn’t as expected, then we have found a fault on the isolated wire

Fault Propagation b/0 w1 w2 b h g f w3 w4 c k D w1 w2 1 f w3 w4

Fault Propagation w1 w2 b h g g/1 f w3 w4 c k 1 w1 w2 D D f w3 w4

Tree Structured Circuits
To test inputs stuck-at-0 at given AND gate Set inputs at other gates to generate AND output of zero Force inputs at selected gate to generate a one If f is 1 then circuit ok, else fault To test inputs stuck-at-1 at given AND gate Drive input to test to 0, rest of inputs driven to 1 Other gates driven with inputs that force gates to 0 If f is 0 then OK, else fault w1 w3 w4 w2 w3 w4 f w1 w2 w3

Product Term Test Stuck-at-0 w1 1 w3 1 w4 1 w2 1 w3 1 w4 1 w1 1 w2 1 w3 1 w1 1 w2 1 w3 1 w4 1 1 w1 w3 w4 1 2 3 4 5 6 7 8 Stuck-at-0 w2 w3 w4 f Stuck-at-1 w1 w2 w3

Product Term Test Stuck-at-1 w1 1 w3 1 w4 1 w2 1 w3 1 w4 1 w1 1 w2 1 w3 1 w1 1 w2 1 w3 1 w4 1 1 w1 w3 w4 1 2 3 4 5 6 7 8 Stuck-at-0 w2 w3 w4 1 f 1 Stuck-at-1 w1 w2 w3

Product Term Test Stuck-at-1 w1 1 w3 1 w4 1 w2 1 w3 1 w4 1 w1 1 w2 1 w3 1 w1 1 w2 1 w3 1 w4 1 1 w1 w3 w4 1 2 3 4 5 6 7 8 Stuck-at-0 w2 w3 w4 1 f 1 Stuck-at-1 w1 w2 w3 Any other stuck-at-1 cases covered?

Product Term Test Stuck-at-1 w1 1 w3 1 w4 1 w2 1 w3 1 w4 1 w1 1 w2 1 w3 1 w1 1 w2 1 w3 1 w4 1 1 w1 w3 w4 1 2 3 4 5 6 7 8 Stuck-at-0 w2 w3 w4 1 f 1 Stuck-at-1 w1 w2 w3 Any other stuck-at-1 cases covered? Was that case already covered?

Product Term Test Stuck-at-1 w1 1 w3 1 w4 1 w2 1 w3 1 w4 1 w1 1 w2 1 w3 1 w1 1 w2 1 w3 1 w4 1 1 w1 w3 w4 1 2 3 4 5 6 7 8 Stuck-at-0 w2 w3 w4 1 f 1 Stuck-at-1 w1 w2 w3 All inputs stuck-at-1’s covered now

Small number of tests has reasonable probability of finding the fault
Random Testing So far: deterministic testing(确定性) 电路中的同一个缺陷为许多输入图形所覆盖，检测出这样一个缺陷只需要这些矢量中的一个，而其他矢量是冗余的。 Alternative: random testing Generate random input patterns to distinguish between the correct function and the faulty function 放宽必须检测出所有缺陷这一要求可以大大减少矢量的数目。为此一般的测试过程只要求95-99%的故障覆盖率。 Probability Fault Detected Small number of tests has reasonable probability of finding the fault Number of Tests

Sequential Testing Due to embedded state inside flip-flops, it is difficult to employ the same methods as with combinational logic 为了测试一个状态机中一定的故障仅仅应用正确的输入激励是不够的。因为首先必须使这个被测部件处于所希望的状态。这需要应用一系列的输入。同时把电路响应传送到其中的输出上。测试一个FSM中的单个缺陷需要一系列的测试向量。 Alternative approach: design for test Scan Path technique: FF inputs pass through multiplexer stages to allow them to be used in normal mode as well as a special test shift register mode 在测试过程中把反馈回路断开，从而把时序电路变成组合电路。自测试（self-test）

设计可测试性的重要特性设计可测试性的重要特性专门测试（ad hoc test）额外的I/O引线高的可控性。高可观察性
只利用输入引线就可以使一个电路节点进入某一指定状态如果只用一个输入向量就可以把一个节点带到任何状态，那么容易控制一个具有低可控性的节点或电路需要一个很长的向量序列才能到预期的状态。高可观察性在输出引线上观察一个节点的值对于一个具有高可观察性的节点，可以在输出引线上直接监测到它的值一个低可观察性的节点则需要多个周期才能使的状态出现在输出口上。当电路的复杂性和引线数目一定时，一个可测电路应当具有较高的可观察性。专门测试（ad hoc test）同应用类型相关集合了一些可用来提高设计的可观察性和可控性的技术额外的I/O引线为了减少可能需要的额外压焊块的数目，可以采用在同一个压焊块上分路选择测试信号和功能信号的方法。 I/O总线在正常工作期间作为数据总线，而在测试期间则用来提供测试图形和收集响应。

Design for Testability
Basic idea Convert a sequential circuit into a combinational circuit Control every flip-flop content Observe every flip-flop output How? Connect flip-flops into one or more shift registers SCAN Design for Testability (Scan DFT) Other benefits Diagnosis & debug Low cost test equipment

Scan Path Technique扫描测试
串联扫描方式 Configure FFs into shift register mode (red path) Scan in test pattern of 0s and 1s Non-state inputs can also be on the scan path (think synchronous Mealy Machine) 激励向量通过引线ScanIn输入逻辑模块 Run system for one clock cycle in “normal” mode (black path)—next state captured in scan path 结果锁存到寄存器中 Return to shift register mode and shift out the captured state and outputs 寄存器中的结果通过引线ScanOut送出电路并与期望的数据进行比较。 Combinational Logic 激励向量

Scan Path Example w,y1,y2 test vector 001 Q D Q D
Scan 01 into y1, y2 FFs w Y1 Y2 Scan-out z y1 y2 D Q 1 D Q 1 Scan-in G/S

Scan Path Example w,y1,y2 test vector 001 Q D Q D 1
Scan 01 into y1, y2 FFs w Y1 Y2 Scan-out z y1 y2 D Q 1 D Q 1 1 Scan-in G/S

Scan Path Example w,y1,y2 test vector 001 Q D Q D 1 1
Scan 01 into y1, y2 FFs w Y1 Y2 Scan-out z y1 y2 D Q 1 D Q 1 1 1 Scan-in G/S

Scan Path Example w,y1,y2 test vector 001 Q D Q D 1 1
Scan 01 into y1, y2 FFs Normal w=0 w Y1 Y2 Scan-out z y1 y2 D Q 1 D Q 1 1 1 Scan-in G/S

Scan Path Example w,y1,y2 test vector 001 Q D Q D 1
Scan 01 into y1, y2 FFs Normal w=0 Output z=0, Y1=0, Y2=0 w Y1 Y2 Scan-out z y1 y2 D Q 1 D Q 1 1 Scan-in G/S

Scan 01 into y1, y2 FFs Normal w=0 Output z=0, Y1=0, Y2=0 Observe z directly w Y1 Y2 Scan-out z y1 y2 D Q 1 D Q 1 Scan-in G/S

Scan 01 into y1, y2 FFs Normal w=0 Output z=0, Y1=0, Y2=0 Observe z directly Scan out Y1, Y2 w Y1 Y2 Scan-out z y1 y2 D Q 1 D Q 1 Scan-in G/S

Scan Operations Scan-in: test pattern shifted in
Apply Test Mode = 1 Number of clock cycles applied in this mode = number of flip-flops in scan chain (shift register) • Apply primary inputs • Capture: combinational logic response to the test pattern captured in flip-flops Apply Test Mode = 0, and 1 or more clock cycles • Observe primary outputs • Scan-out: captured response shifted out Number of clock cycles applied in this mode = number of flip-flops In· scan chain (shift register)

部分扫描并不是设计中所有的寄存器都需要扫描流水线寄存器只是为了提高性能，并不增加电路的新状态只需使输入和输出寄存器可扫描就可以了

边界扫描设计（boundary scan）
把一个板上部件的输入-输出引线连接成一条串联的扫描链在正常工作时，边界扫描压焊块pads作为正常的输入-输出器件在测试模式，向量可以从这些压焊块处扫入扫出，从而在部件的边界上提供可控性和可观察性。可以利用各种控制模块来测试各个部件以及板上的互连线。这方法的开销是要求稍微复杂一些的输入-输出压焊块以及一个附加的片上测试控制器。目前大多数产品部件都提供边界扫描。板级测试的边界扫描方法

边界扫描链边界扫描链由边界扫描单元串行组成边界扫描单元能够完成对电路节点的控制和观察功能边界扫描单元的结构

为了实现PCB测试，芯片的边界扫描链要求必须在所有的管脚添加边界扫描单元。
对于输入管脚、两态输出管脚、三态输出管脚和双向管脚，边界扫描单元添加方式有所不同当不实现INTEST指令时，输入管脚的边界扫描单元只用一个观察级的扫描单元即可，当需要实现INTEST指令时，还必须添加一个带控制级的扫描单元。

两态的输出管脚必须添加带输出锁存的边界扫描单元

三态输出管脚除了添加带输出锁存的边界扫描单元外，还必须在三态控制信号上也添加一个带输出锁存的边界扫描单元
双向边界扫描单元由一个三态输出扫描单元和一个只带观察级的输入扫描单元组成

边界扫描除了在管脚上添加边界扫描单元外，为了实现芯片内部的电路级可测试性，还必须在内部的电路节点添加扫描单元。
扫描单元一般添加在寄存器的位置，用带扫描功能的寄存器替换设计中的所有寄存器，即可实现全扫描设计。全扫描资源消耗很大，同时扫描链过长也使得串行数据扫描的速度急剧下降，使得测试速度变慢。需要根据电路逻辑结构采用部分扫描设计。

Built-in Self-Test (BIST)内建测试
Vector Generator Circuit Under Response Compressor x0 . xn-1 P0 Pm-1 Signature 内建自测试让电路自己生成测试图形电路自己能够决定它所得到的测试结果是否正确 Test Vector Generator Pseudorandom tests with a feedback shift register 穷尽测试，所有可以得到的输入信号空间，所有可测的故障都会被检测到。对于N值较大的电路，通过整个输入空间的操作所需要的时间是无法接受的。 Seed generates a sequence of test patterns Outputs combined using the same technique Generates a unique signature签名 that can be checked to determine if the circuit is correct 原则是应当能得到合理的故障覆盖率

Linear Feedback Shift Register
由多个一位的寄存器串联构成把这个寄存器初始化为一定的种子值就会产生不同的伪随机序列。 D Q D Q D Q D Q 有些输出被异或（XOR）并反馈回移位寄存器的输入 Random Test Pattern P D Q D Q D Q D Q Input from circuit under test Signature

Q D Q D Q D Q Initial Configuration x3 x2 x1 x0 x3 x2 x1 x0 f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 … … Starting with the pattern 1000种子, generates 15 different patterns in sequence and then repeats Pattern 0000 is a no-no

改进的线性反馈移位寄存器用同一硬件来完成图形生成和信号分析响应分析器将所生成的响应与存放在片上存储器中的预期响应进行比较更经济的技术是在对它们进行比较之前把这些响应进行压缩 Multi-input Compressor 每一个进来的数据字被一个接一个地与LFSR的内容相比较(XOR)。在测试序列结束时，LFSR中含有了这个数据序列的签名或特征字，可以用来与正确电路的特征字进行比较。 Signature D Q P3 P2 P1 P0 Circuit Under Test Outputs

Test Compression • BIST benefits retained, BIST issues avoided
• MAJOR proliferation in the industry • Example configurations: n = 200, p = k = 15; n = 500, p= k = 20; n = 1,000, p = k = 50

一位信号流的压缩签名分析器响应分析器有一个动态压缩被测电路输出的电路以及一个比较器构成。
被压缩的输出也常常称为该电路的签名，而整个方法称为签名分析。这一电路只是计数输入流中0->1和1->0的翻转数目。这一压缩并不能保证接收到的序列是正确的，也就是说许多不同的序列可以有相同数目的翻转。但是翻转数目不对，电路肯定有错。

Test Compression Advantages
• Exponential reduction (50 – 80X, sometimes even more) Test data volume, time, pins, tester channels • High test quality • X tolerance New X-Compactor technique – an example of combining VLSI with information theory • Commercial ATPG tool compatibility • Diagnosis support • Fault model & test set independence • Very little area overhead, no extra delay • Easy automation

Complete Self-Test System
Normal Inputs MIC M U X Combinational Circuit Multi-input Compressor PRBSG Scan out SIC Random Test Sequences FFs and Muxes Single-input Compressor Scan in PRBSG Random Test Sequences

Built-in Logic Block Observer (Bilbo)内建逻辑块监测器
EE141 Built-in Logic Block Observer (Bilbo)内建逻辑块监测器 Test generation and compression in a single circuit! M1, M2 = 11: Regular mode M1, M2 = 00: Shift register mode扫描移位寄存器 M1, M2 = 10: Signature generation mode签名分析/模式产生 M1, M2 = 01: Reset mode 1 M1 P3 D Q P2 D Q P1 D Q P0 D Q M2 Sin 1 G/S Q3 Q2 Q1 Q0 Normal/Scan Sout

Bilbo Architecture Scan-out Combinational Network CN1 Combinational
EE141 Bilbo Architecture Scan-out Combinational Network CN1 Combinational Network CN2 BILBO1 BILBO2 Scan-in Scan initial pattern in Bilbo1, reset FFs in Bilbo2 Use Bilbo1 as PRBS探测信号 generator for given number of clock cycles and use Bilbo2 to produce signature Scan out Bilbo2 and compare signature; Scan in initial test pattern for CN2; Reset the FFs in Bilbo1 Use Bilbo2 as PRBS generator for a given number of clock cycles and use Bilbo1 to produce signature Scan out Bilbo1 and compare signature;

内建逻辑块监测（BILBO）

系统芯片测试方法片上系统时代的到来并未使测试工作变得更简单一些。内建自测试应当是解决这一问题的惟一方法。
BIST自测试方法允许测试以实际的时钟速度运行，减少了测试时间

Summary Fault models故障模型 Scan Path扫描路径 Built-in Test内建测试
Approach for determining how to develop a test pattern sequence Weakness is the single fault assumption Scan Path扫描路径 Technique for applying test inputs deep within the system, usually for asserting state Technique for getting internal state to edges of circuit for observation Built-in Test内建测试 Founded on the approach of random testing Generate pseudo random sequences; compute signature; determine if signature generated is same as signature of a correctly working circuity

课后作业 1）查阅： 2）作业： 3）阅读：国际电路公司的
EE141 课后作业 1）查阅：国际电路公司的 8051，PIC，AVR单片机, ARM，MIPS，DSP等微控制器芯片的型号、类型、速度…… 图书馆资源：电子器件天地, 软件 2）作业：见学在浙里题目 3）阅读：复习《数字系统设计与Verilog HDL》书CH.11

EE141 课后作业 4）Project Project1（必做）：将讲义P31页图8.33的框图用具体型号的数字集成电路设计实现为具体电路图。（6月6日交报告和电路图） Project2（选做平时成绩加分）：用具体逻辑电路描述设计并FPGA实现一个4bit简单CPU实物。（期末停课前完成） Spring – Lec. #10

4bit Simple CPU ALU 时钟 PC计数器寄存器程序存储器寄存器组总线 Spring – Lec. #10

4bit Simple CPU Spring – Lec. #10

参考资料 Spring – Lec. #10

数字系统设计 Digital System Design

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数字系统设计 Digital System Design

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