组合逻辑3 Combinational Logic

Presentation on theme: "组合逻辑3 Combinational Logic"— Presentation transcript:

1 组合逻辑3 Combinational Logic
刘鹏 浙江大学信息与通信工程研究所 Multiplexers: Two-to-one-line, Four-to-one-line multiplexer, 74HC153, March 24, 2015 ZDMC – Lec. #5

2 复习 本节内容 选择器Multiplexer 加法器Adder 比较器Comparator 采用模块组件实现组合电路 显示译码器 竞争和冒险
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3 复习 数据选择器 Multiplexers 数据选择器是从多路输入线中选择其中的一路到输出线的一种组合电路。 二选一数据选择器：
数据输入线D0-D1 选择线A0 输出线Y 电路图 表达式：Y=A0’D0+A0D1 ZDMC – Lec. #5

4 复习 4选1 Multiplexer 四选一数据选择器逻辑图 功能表 A1 A0 Y D0 1 D1 D2 D3 逻辑函数式
D0 1 D1 D2 D3 逻辑函数式 Y= A1’A0’D0+A1’A0D1+A1A0’D2+A1A0D3 ZDMC – Lec. #5

5 例：74HC153,两个“四选一”接成“八选一” “四选一”只有2位地址输入，从四个输入中选中一个
“八选一”的八个数据需要3位地址代码指定其中任何一个 ZDMC – Lec. #5

6 74LS151 74LS151 I0 I1 I2 I3 I4 I5 I6 I7 S2 S1 S0 E’ Z Z’
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7 16-input multiplexer Two 74HC151s combined to form a 16-input multiplexer Two 74HC151s combined to form a 16-input multiplexer ZDMC – Lec. #5

8 复习 采用数据选择器设计组合电路 基本原理 Y= D0A1’A0’ +D1A1’A0+D2A1A0’ + D3A1A0
具有n-1位地址输入的数据选择器，可实现n个变量布尔函数。 数据选择器就是一个带或（OR） 门的译码器 ZDMC – Lec. #5

9 选择器实现逻辑功能 Multiplexers implement logic functions
An eight-input multiplexer can be used to implement the logic circuit that satisfies the given truth table. ZDMC – Lec. #5

10 复习 加法器：半加器Half Adder, HA 半加器，不考虑来自低位的进位，将两个1位的二进制数相加.
我们指定符号S(for sum) and CO(for carry) to the outputs。 输入为A和B。 真值表the truth table 输 入 输 出 A B S CO 1 一个异或门和一个与门 ZDMC – Lec. #5

11 复习 全加器Full Adder, FA 将两个1位二进制数A,B及来自低位的进位CI相加 输 入 输 出 A B CI S CO 1
输 入 输 出 A B CI S CO 1 74LS183 74HC183 ZDMC – Lec. #5

12 复习 用加法器设计组合电路 基本原理： 若能生成函数可变换成输入变量与输入变量相加 若能生成函数可变换成输入变量与常量相加
例：将BCD的8421码转换为余3码 输 入 输 出 D C B A Y3 Y2 Y1 Y0 1 ZDMC – Lec. #5

13 数值比较器 MAGNITUDE COMPARATOR
复习 数值比较器 MAGNITUDE COMPARATOR 用来比较两个二进制数的数值大小 一、1位数值比较器 A,B比较有三种可能结果 ZDMC – Lec. #5

14 多位数值比较器 原理：从高位比起，只有高位相等，才比较下一位。 例如： ZDMC – Lec. #5

15 Four-bit Magnitude Comparator 4位比较器
复习 Four-bit Magnitude Comparator 4位比较器 Three active-HIGH outputs. ZDMC – Lec. #5

16 复习 4-位比较器的真值表 ZDMC – Lec. #5

17 复习 4位比较器 ZDMC – Lec. #5

18 复习 8-bit 比较 ZDMC – Lec. #5

19 显示译码器 1. 七段字符显示器 如： ZDMC – Lec. #5

20 2. BCD七段字符显示译码器 （代码转换器）7448 输 入 输 出 数字 A3 A2 A1 A0 Ya Yb Yc Yd Ye Yf
输 入 输 出 数字 A3 A2 A1 A0 Ya Yb Yc Yd Ye Yf Yg 字形 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ZDMC – Lec. #5

21 BCD-to-7段译码器/驱动共阳极7段LED显示
A common-anode type, the anodes of all of the segments are tied together to Vcc. A common-cathode arrangement where the cathodes of all of the segments are tied together and connected to ground. Each segment of a typical 7-segment LED display is rated to operate at 10mA at 2.7V for normal brightness. Calculate the value of the current-limiting resistor needed to produce approximately 10mA per segment. Rs=2.3V/10mA=230Ω ZDMC – Lec. #5

22 Troubleshooting(故障查找)
Crossed the connections to the e and f segments. As circuits and systems become more complex, the number of possible causes of failure obviously increases. Whereas the procedure for fault isolation and correction remains essentially the same, the application of the observation/analysis process is more important for complex circuits because it helps the troubleshooter narrow the location of the fault to a small area of the circuit. Observing the symptoms of the failure, and reasoning through the operation, the troubleshooter can often predict the possible faults before ever picking up a logic probe or an oscilloscope. Another vital strategy in troubleshooting is known as divide-and-conquer. ZDMC – Lec. #5

23 Troubleshooting(故障查找)
Comparing the observed display with the expected display for each count, we see several important points: The correct segment patterns (0,1,3,67,and 8) have the common property that segments e and f are either both on or both off. The incorrect segment patterns have the common property that segments e and f are in opposite states, and if we interchange the states of these two segments, the correct pattern is obtained. “Crossed” the connections to the e and f segments. As circuits and systems become more complex, the number of possible causes of failure obviously increases. Whereas the procedure for fault isolation and correction remains essentially the same, the application of the observation/analysis process is more important for complex circuits because it helps the troubleshooter narrow the location of the fault to a small area of the circuit. Observing the symptoms of the failure, and reasoning through the operation, the troubleshooter can often predict the possible faults before ever picking up a logic probe or an oscilloscope. Another vital strategy in troubleshooting is known as divide-and-conquer. ZDMC – Lec. #5

24 组合逻辑电路中的竞争-冒险现象 竞争-冒险现象及成因 一、什么是“竞争” 两个输入“同时向相反的逻辑电平变化”，称存在“竞争”
二、因“竞争”而可能在输出产 生尖峰脉冲的现象，称为 “竞争-冒险”。 ZDMC – Lec. #5

25 2线—4线译码器中的竞争-冒险现象 ZDMC – Lec. #5

26 消除竞争-冒险现象的方法 一、接入滤波电容 尖峰脉冲很窄，用很小的电容就可将尖峰削弱到 VTH 以下。 二、引入选通脉冲
取选通脉冲作用时间，在电路达到稳定之后，P的高电平期的输出信号不会出现尖峰。 ZDMC – Lec. #5

27 三、修改逻辑设计 例： ZDMC – Lec. #5

28 概括 (Recap) 组合电路的基本模块 译码器、编码器、选择器、加法器、比较器 采用基本模块来设计组合电路 组合电路的竞争和冒险
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29 Encoder octal-to-binary (8-line-to-3-line) encoder
For proper operation, only one input should be active at one time. A3’ and A5’ are simultaneously LOW The binary code 111. Clearly, this is not the code for either activated input. ZDMC – Lec. #5

30 Priority Encoder (74147 decimal-to-BCD)
The outputs will normally the HIGH when none of the inputs are activated. This corresponds to the decimal 0 input condition. ZDMC – Lec. #5

31 Multiplexers (Data Selectors)
Functional diagram of a digital multiplexer (MUX) The outputs will normally the HIGH when none of the inputs are activated. This corresponds to the decimal 0 input condition. ZDMC – Lec. #5