时序电路设计 刘鹏 浙江大学信息与电子工程系 Apr. 24, 2011 EE141

Presentation on theme: "时序电路设计 刘鹏 浙江大学信息与电子工程系 Apr. 24, 2011 EE141"— Presentation transcript:

1 时序电路设计 刘鹏 liupeng@zju.edu.cn 浙江大学信息与电子工程系 Apr. 24, 2011 EE141
Winter ZDMC – Lec. #1 – 1

2 例：设计一个串行数据检测器，要求在连续输入三个或三个以上“1”时输出为1，其余情况下输出为0。
EE141 例：设计一个串行数据检测器，要求在连续输入三个或三个以上“1”时输出为1，其余情况下输出为0。 一、抽象、画出状态转换图 二、状态化简 用X（1位）表示输入数据 用Y（1位）表示输出（检测结果） Winter ZDMC – Lec. #1 – 2

3 EE141 三、状态分配 取n=2，令 的00、01、10为 则， Winter ZDMC – Lec. #1 – 3

4 EE141 四、选用JK触发器，求方程组 五、画逻辑图 Winter ZDMC – Lec. #1 – 4

5 将状态“11” 代入状态方程和输出方程，分别求X=0/1下的次态和现态下的输出，得到：
EE141 六、检查电路能否自启动 将状态“11” 代入状态方程和输出方程，分别求X=0/1下的次态和现态下的输出，得到： 能自启动 Winter ZDMC – Lec. #1 – 5

6 Example: Ant Brain Sensors: L and R antennae, 1 if in touching wall
EE141 Example: Ant Brain Sensors: L and R antennae, 1 if in touching wall Actuators: F - forward step, TL/TR - turn left/right slightly Goal: find way out of maze Strategy: keep the wall on the right Winter ZDMC – Lec. #1 – 6

7 EE141 Ant Brain Winter ZDMC – Lec. #1 – 7

8 EE141 Ant Behavior A: Following wall, touching Go forward, turning left slightly B: Following wall, not touching Go forward, turning right slightly D: Hit wall again Back to state A C: Break in wall Go forward, turning right slightly E: Wall in front Turn left until... F: ...we are here, same as state B G: Turn left until... LOST: Forward until we touch something Winter ZDMC – Lec. #1 – 8

9 Designing an Ant Brain State Diagram L + R L’ R LOST (F) L’ R’
EE141 Designing an Ant Brain State Diagram L + R L’ R LOST (F) L’ R’ E/G (TL) L + R R A (TL, F) L L’ R’ B (TR, F) L’ R’ R C (TR, F) R’ R’ Winter ZDMC – Lec. #1 – 9

10 Synthesizing the Ant Brain Circuit
EE141 Synthesizing the Ant Brain Circuit Encode States Using a Set of State Variables Arbitrary choice - may affect cost, speed Use Transition Truth Table Define next state function for each state variable Define output function for each output Implement next state and output functions using combinational logic 2-level logic (ROM/PLA/PAL) Multi-level logic Next state and output functions can be optimized together Winter ZDMC – Lec. #1 – 10

11 Transition Truth Table
EE141 Transition Truth Table Using symbolic states and outputs LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’ L’ R’ R L L’ R L + R state L R next state outputs LOST 0 0 LOST F LOST – 1 E/G F LOST 1 – E/G F A 0 0 B TL, F A 0 1 A TL, F A 1 – E/G TL, F B – 0 C TR, F B – 1 A TR, F Winter ZDMC – Lec. #1 – 11

12 Synthesis 5 states : at least 3 state variables required (X, Y, Z)
EE141 Synthesis 5 states : at least 3 state variables required (X, Y, Z) State assignment (in this case, arbitrarily chosen) LOST - 000 E/G - 001 A - 010 B - 011 C - 100 state L R next state outputs X,Y,Z X', Y', Z' F TR TL it now remains to synthesize these 6 functions Winter ZDMC – Lec. #1 – 12

13 Synthesis of Next State and Output Functions
EE141 Synthesis of Next State and Output Functions state inputs next state outputs X,Y,Z L R X+,Y+,Z+ F TR TL e.g. TR = X + Y Z X+ = X R’ + Y Z R’ = R’ TR Winter ZDMC – Lec. #1 – 13

14 Circuit Implementation
EE141 Circuit Implementation Outputs are a function of the current state only - Moore machine L R F TR TL Next State Current State output logic next state logic X+ Y+ Z+ X Y Z Winter ZDMC – Lec. #1 – 14

15 Verilog Sketch module ant_brain (F, TR, TL, L, R) inputs L, R;
EE141 Verilog Sketch module ant_brain (F, TR, TL, L, R) inputs L, R; outputs F, TR, TL; reg X, Y, Z; assign F = function(X, Y, Z, L, R); assign TR = function(X, Y, Z, L, R); assign TL = function(X, Y, Z, L, R); clk) begin X <= function (X, Y, Z, L, R); Y <= function (X, Y, Z, L, R); Z <= function (X, Y, Z, L, R); end endmodule Winter ZDMC – Lec. #1 – 15

16 Don’t Cares in FSM Synthesis
EE141 Don’t Cares in FSM Synthesis What happens to the "unused" states (101, 110, 111)? Exploited as don't cares to minimize the logic If states can't happen, then don't care what the functions do if states do happen, we may be in trouble 000 (F) 001 (TL) 010 (TL, F) 011 (TR, F) 100 (TR, F) R’ L’ R’ R L L’ R L + R 111 101 110 Ant is in deep trouble if it gets in this state Winter ZDMC – Lec. #1 – 16

17 State Minimization Fewer states may mean fewer state variables
EE141 State Minimization Fewer states may mean fewer state variables High-level synthesis may generate many redundant states Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same Two conditions for two states to be equivalent: 1) Output must be the same in both states 2) Must transition to equivalent states for all input combinations Winter ZDMC – Lec. #1 – 17

18 Ant Brain Revisited Any equivalent states? LOST (F) E/G (TL) A (TL, F)
EE141 Ant Brain Revisited Any equivalent states? LOST (F) E/G (TL) A (TL, F) B (TR, F) C (TR, F) R’ L’ R’ R L L’ R L + R Winter ZDMC – Lec. #1 – 18

19 New Improved Brain Merge equivalent B and C states
Behavior is exactly the same as the 5-state brain We now need only 2 state variables rather than 3 LOST (F) E/G (TL) A (TL, F) B/C (TR, F) R’ L’ R’ R L L’ R L + R Winter ZDMC – Lec. #1 – 19

20 New Brain Implementation
EE141 New Brain Implementation state inputs next state outputs X,Y L R X',Y' F TR TL X X+ Y R L X Y+ Y R L X F Y R L X TR Y R L X TL Y R L Winter ZDMC – Lec. #1 – 20

21 Design hierarchy system data-path control code registers
EE141 Design hierarchy system data-path control code registers state registers combinational logic multiplexer comparator register logic switching networks Winter ZDMC – Lec. #1 – 21

22 常用时序电路模块的设计 C1 1D Q D CLK 1.最简单的D触发器 module DFF( output Q , input D ,
input CLK); reg Q; CLK) begin Q <=D; end endmodule Winter ZDMC – Lec. #1 – 22

23 2.带异步清0、异步置1的D触发器 不需要同步输入端D。与组合差别？ C1 1D R d clk reset q S set qn
module DFF1(q,qn,d,clk,set,reset); input d, clk, set, reset; output q, qn; reg q, qn; clk or negedge set or negedge reset) begin if (! reset) begin q <=0; qn <= 1; end //异步清0，低电平有效 else if (! set ) begin q<=1; qn<=0; end //异步置1，低电平有效 else begin q <=d; qn <= ~d; end end endmodule 不需要同步输入端D。与组合差别？ C1 1D R d clk reset q S set qn Winter ZDMC – Lec. #1 – 23

24 3.带同步清0、同步置1的D触发器 注意：清0和置1，同步与异步差别？ C1 1D 1R d clk reset q 1S set qn
module DFF2(q, qn, d, clk, set, reset); input d, clk, set, reset; output q, qn; reg q, qn; (posedge clk) begin if(reset) begin q <=0; qn <=1; end //同步清0，高电平有效 else if (set) begin q <=1;qn <=0; end //同步置1，高电平有效 else begin q <= d; qn <= ~d; end end endmodule 注意：清0和置1，同步与异步差别？ C1 1D 1R d clk reset q 1S set qn Winter ZDMC – Lec. #1 – 24

25 数据锁存器 1.电平敏感的一位数据锁存器(同步D） C1 1D q d clk 2.带置位和复位端的1位数据锁存器 q C1 1D 1R d
module latch_1(q, d, clk); output q; input d, clk; assign q =clk ? d : q; //时钟高电平时，将输入端数据锁存 endmodule 2.带置位和复位端的1位数据锁存器 q C1 1D 1R d clk reset 1S set module latch_2(q, d, clk, set, reset); output q; input d, clk, set, reset; assign q =reset ? 0 : (set ? 1 :(clk ? d : q) ); endmodule Winter ZDMC – Lec. #1 – 25

26 8位数据锁存器 C1 1D qout data clk 8 module latch_8(qout, data, clk);
output[7:0] qout; input[7:0] data; input clk; reg[7:0] qout; (clk or data) begin if(clk) qout =data; end endmodule clk高电平有效， 当clk=1时：输出、输入是透明。 Winter ZDMC – Lec. #1 – 26

27 8位数据寄存器 C1 1D out_data in_data clk 8 clr R 数据锁存器与数据寄存器的差别？
module reg8(out_data,in_data,clk,clr); output[7:0] out_data; input clk,clr; input[7:0] in_data; reg[7:0] out_data; (posedge clk or posedge clr) begin if(clr) out_data <=0; else out_data <= in_data; end endmodule C1 1D out_data in_data clk 8 clr R 数据锁存器与数据寄存器的差别？ 电平触发 边沿触发 Winter ZDMC – Lec. #1 – 27

28 SRG8 clr 1R clk C1/ din dout1 1D dout8 移位寄存器（单向）
module shifter(din , clk , clr ,dout); parameter n=8; input din , clk , clr; output[8:1] dout ; reg[8:1] dout; clk) begin if (clr) dout <= 0; // 同步清0，高电平有效 else begin dout <= dout << 1;//输出信号左移一位 dout[1] <= din; //输入信号补充到输出信号的最低位 end endmodule Winter ZDMC – Lec. #1 – 28

29 CTR8 clr R load cout cin clk 8 data out 可预置的n位二进制计数器（带异步清0） 计数器
M1 M2 G3 C4/2,3+ 8 3CT=255 1,4D load cin clk data out cout clr R module counter_n (out, cout, data, load, cin ,clr, clk); parameter n=8; output [n:1] out; output cout; input load, cin, clr, clk; input [n:1] data; reg [n:1] out; clk or negedge clr) //异步清0 begin if(!clr) out<=0; else if (load) out<= data;//置数 else out <= out + cin; //计数或保持 end assign cout=&out&cin; // 进位 endmodule 计数器的位数 Winter ZDMC – Lec. #1 – 29

30 n:模；size：计数器位数 任意进制计数器（带异步清0） module n_counter (Q, CO, EN ,CLR, CLK);
parameter n=30; parameter size=5; output [size:1] Q; output CO; input EN ,CLR, CLK; reg [size:1] Q; CLK or negedge CLR) //异步清0 begin if(!CLR) Q<=0; else if(Q==(n-1)) Q<=EN?0:Q; //计数或保持 else Q <= Q + EN; //计数或保持 end assign CO=(Q==(n-1))&EN; // 进位 endmodule Winter ZDMC – Lec. #1 – 30

31 CTR8 clr 5CT=0 load up_down clk 8 d qd 可预置的加减计数器 M1 M2 M3(dn) C5/ 1,4D
M4(up) 1,4+;1,3- 5CT=0 module up_down_count(d,clk,clear,load,up_down,qd); parameter size=8; input[size:1] d; input clk,clear,load,up_down ; output[size:1] qd; reg[size:1] cnt; assign qd=cnt; clk) begin if(!clear) cnt<=0;//低电平、同步复位 else if(load) cnt<=d;//高电平、同步置数 else if(up_down) cnt<=cnt+1;//加法计数 else cnt<=cnt-1;//减法计数 end endmodule Winter ZDMC – Lec. #1 – 31

32 BCD码计数器 module count60(qout,cout,data,load,cin,reset,clk);
parameter MODULUS=8'h23; output[7:0] qout; output cout; input[7:0] data; input load,cin,reset,clk; reg [7:0] qout; assign cout=(qout==MODULUS)&cin;//进位 clk) begin if(reset) qout<=0; else if(load) qout<=data;//同步置数 else if(cin) //cin=1,计数cin=0,保持 begin if(qout==MODULUS) qout<=0 ; else if (qout[3:0]==9)begin qout[3:0]<=0; qout[7:4]<=qout[7:4]+1; end else qout[3:0]<=qout[3:0]+1; endmodule 改变MODULUS的值（<=100)，即可改变模 Winter ZDMC – Lec. #1 – 32

33 Sequential Logic Implementation Summary
EE141 Sequential Logic Implementation Summary Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic Winter ZDMC – Lec. #1 – 33

34 Sequential Logic Implementation
EE141 Sequential Logic Implementation Models for representing sequential circuits Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure Verilog specification Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic Winter ZDMC – Lec. #1 – 34