Verilog HDL 硬件描述语言 刘鹏 浙江大学信息与电子工程系 Mar. 6, 2012

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1 Verilog HDL 硬件描述语言 刘鹏 liupeng@zju.edu.cn 浙江大学信息与电子工程系 Mar. 6, 2012
EE141 Verilog HDL 硬件描述语言 刘鹏 浙江大学信息与电子工程系 Mar. 6, 2012 Winter ZDMC – Lec. #1 – 1

2 HDLs “Structural” example: “Behavioral” example: Basic Idea:
EE141 HDLs “Structural” example: Decoder(output x0,x1,x2,x3; inputs a,b) { wire abar, bbar; inv(bbar, b); inv(abar, a); nand(x0, abar, bbar); nand(x1, abar, b ); nand(x2, a, bbar); nand(x3, a, b ); } “Behavioral” example: case [a b] 00: [x0 x1 x2 x3] = 0x0; 01: [x0 x1 x2 x3] = 0x2; 10: [x0 x1 x2 x3] = 0x4; 11: [x0 x1 x2 x3] = 0x8; endcase; Basic Idea: Language constructs describe circuits with two basic forms: Structural descriptions similar to hierarchical netlist. Behavioral descriptions use higher-level constructs (similar to conventional programming). Originally designed to help in abstraction and simulation. Now “logic synthesis” tools exist to automatically convert from behavioral descriptions to gate netlist. Greatly improves designer productivity. However, this may lead you to falsely believe that hardware design can be reduced to writing programs! Winter ZDMC – Lec. #1 – 2

3 Design Methodology HDL Specification Simulation Synthesis
EE141 Design Methodology HDL Specification Structure and Function (Behavior) of a Design Simulation Synthesis Verification: Design Behave as Required? Functional: I/O Behavior Register-Level (Architectural) Logic-Level (Gates) Transistor-Level (Electrical) Timing: Waveform Behavior Generation: Map Specification to Implementation Winter ZDMC – Lec. #1 – 3

4 Quick History of HDLs ISP (circa 1977) - research project at CMU
EE141 Quick History of HDLs ISP (circa 1977) - research project at CMU Simulation, but no synthesis Abel (circa 1983) - developed by Data-I/O Targeted to programmable logic devices Not good for much more than state machines Verilog (circa 1985) - developed by Gateway (now Cadence) Similar to Pascal and C, originally developed for simulation Fairly efficient and easy to write 80s Berkeley develops synthesis tools IEEE standard VHDL (circa 1987) - DoD sponsored standard Similar to Ada (emphasis on re-use and maintainability) Simulation semantics visible Very general but verbose Winter ZDMC – Lec. #1 – 4

5 Verilog Supports structural and behavioral descriptions Structural
EE141 Verilog Supports structural and behavioral descriptions Structural Explicit structure of the circuit How a module is composed as an interconnection of more primitive modules/components E.g., each logic gate instantiated and connected to others Behavioral Program describes input/output behavior of circuit Many structural implementations could have same behavior E.g., different implementations of one Boolean function Winter ZDMC – Lec. #1 – 5

6 Verilog Introduction the module describes a component in the circuit
EE141 Verilog Introduction the module describes a component in the circuit Two ways to describe: Structural Verilog List of components and how they are connected Just like schematics, but using text A net list tedious to write, hard to decode Essential without integrated design tools Behavioral Verilog Describe what a component does, not how it does it Synthesized into a circuit that has this behavior Result is only as good as the tools Build up a hierarchy of modules Winter ZDMC – Lec. #1 – 6

7 By default, identifiers are wires
EE141 Structural Model - XOR port list module name declarations statements Built-in gates interconnections module xor_gate ( out, a, b ); input a, b; output out; wire abar, bbar, t1, t2; inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2); endmodule a and1 t1 out invB or1 t2 and2 b Instance name invA Composition of primitive gates to form more complex module Note use of wire declaration! By default, identifiers are wires Winter ZDMC – Lec. #1 – 7

8 Structural Model: 2-to1 mux
EE141 Structural Model: 2-to1 mux Notes: comments “module” port list declarations wire type primitive gates Instance names? List per type //2-input multiplexor in gates module mux2 (in0, in1, select, out); input in0,in1,select; output out; wire s0,w0,w1; not (s0, select); and (w0, s0, in0), (w1, select, in1); or (out, w0, w1); endmodule // mux2 Winter ZDMC – Lec. #1 – 8

9 Simple Behavioral Model
EE141 Simple Behavioral Model Combinational logic Describe output as a function of inputs Note use of assign keyword: continuous assignment module and_gate (out, in1, in2); input in1, in2; output out; assign out = in1 & in2; endmodule Output port of a primitive must be first in the list of ports Restriction does not apply to modules When is this evaluated? Winter ZDMC – Lec. #1 – 9

10 2-to-1 mux behavioral description
EE141 2-to-1 mux behavioral description Notes: behavioral descriptions use the keyword always followed by blocking procedural assignments Target output of procedural assignments must of of type reg (not a real register) Unlike wire types where the target output of an assignment may be continuously updated, a reg type retains it value until a new value is assigned (the assigning statement is executed). Optional initial statement // Behavioral model of 2-to-1 // multiplexor. module mux2 (in0,in1,select,out); input in0,in1,select; output out; // reg out; (in0 or in1 or select) if (select) out=in1; else out=in0; endmodule // mux2 Sensitivity list Winter ZDMC – Lec. #1 – 10

11 Behavioral 4-to1 mux Notes: //Does not assume that we have
EE141 Behavioral 4-to1 mux Notes: No instantiation Case construct equivalent to nested if constructs. Definition: A structural description is one where the function of the module is defined by the instantiation and interconnection of sub-modules. A behavioral description uses higher level language constructs and operators. Verilog allows modules to mix both behavioral constructs and sub-module instantiation. //Does not assume that we have // defined a 2-input mux. //4-input mux behavioral description module mux4 (in0, in1, in2, in3, select, out); input in0,in1,in2,in3; input [1:0] select; output out; reg out; (in0 in1 in2 in3 select) case (select) 2’b00: out=in0; 2’b01: out=in1; 2’b10: out=in2; 2’b11: out=in3; endcase endmodule // mux4 Winter ZDMC – Lec. #1 – 11

12 Mixed Structural/Behavioral Model
EE141 Mixed Structural/Behavioral Model Example 4-bit ripple adder module full_addr (S, Cout, A, B, Cin ); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin; endmodule module adder4 (S, Cout, A, B, Cin); input [3:0] A, B; input Cin; output [3:0] S; output Cout; wire C1, C2, C3; full_addr fa0 (S[0], C1, A[0], B[0], Cin); full_addr fa1 (S[1], C2, A[1], B[1], C1); full_addr fa2 (S[2], C3, A[2], B[2], C2); full_addr fa3 (S[3], Cout, A[3], B[3], C3); Behavior Structural Order of ports? Winter ZDMC – Lec. #1 – 12

13 Verilog Data Types and Values
EE141 Verilog Data Types and Values Bits - value on a wire 0, 1 X - don’t care/don’t know Z - undriven, tri-state Vectors of bits A[3:0] - vector of 4 bits: A[3], A[2], A[1], A[0] Treated as an unsigned integer value e.g. , A < 0 ?? Concatenating bits/vectors into a vector e.g., sign extend B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]}; B[7:0] = {3{A[3]}, A[3:0]}; Style: Use a[7:0] = b[7:0] + c; Not: a = b + c; // need to look at declaration Winter ZDMC – Lec. #1 – 13

14 Verilog Numbers 14 - ordinary decimal number
EE141 Verilog Numbers 14 - ordinary decimal number ’s complement representation 12’b0000_0100_ binary number with 12 bits (_ is ignored) 12’h hexadecimal number with 12 bits Verilog values are unsigned e.g., C[4:0] = A[3:0] + B[3:0]; if A = 0110 (6) and B = 1010(-6) C = not i.e., B is zero-padded, not sign-extended Winter ZDMC – Lec. #1 – 14

15 EE141 Verilog Operators Winter ZDMC – Lec. #1 – 15

16 Verilog Variables wire reg usage:
EE141 Verilog Variables wire Variable used simply to connect components together reg Variable that saves a value as part of a behavioral description Usually corresponds to a wire in the circuit Is NOT necessarily a register in the circuit usage: Don’t confuse reg assignments with the combinational continuous assign statement! (more soon) Reg should only be used with always blocks (sequential logic, to be presented …) Winter ZDMC – Lec. #1 – 16

17 Verilog Module Corresponds to a circuit component
EE141 Verilog Module Corresponds to a circuit component “Parameter list” is the list of external connections, aka “ports” Ports are declared “input”, “output” or “inout” inout ports used on tri-state buses Port declarations imply that the variables are wires module name ports module full_addr (A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; assign {Cout, S} = A + B + Cin; endmodule inputs/outputs Winter ZDMC – Lec. #1 – 17

18 Verilog Continuous Assignment
EE141 Verilog Continuous Assignment Assignment is continuously evaluated assign corresponds to a connection or a simple component with the described function Target is NEVER a reg variable Dataflow style use of Boolean operators (~ for bit-wise, ! for logical negation) assign A = X | (Y & ~Z); assign B[3:0] = 4'b01XX; assign C[15:0] = 4'h00ff; assign #3 {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin; bits can take on four values (0, 1, X, Z) variables can be n-bits wide (MSB:LSB) use of arithmetic operator multiple assignment (concatenation) delay of performing computation, only used by simulator, not synthesis Winter ZDMC – Lec. #1 – 18

19 EE141 Comparator Example module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign Equal = (A & B) | (~A & ~B); assign Alarger = (A & ~B); assign Blarger = (~A & B); endmodule Winter ZDMC – Lec. #1 – 19

20 EE141 Comparator Example // Make a 4-bit comparator from 4 1-bit comparators module Compare4(A4, B4, Equal, Alarger, Blarger); input [3:0] A4, B4; output Equal, Alarger, Blarger; wire e0, e1, e2, e3, Al0, Al1, Al2, Al3, B10, Bl1, Bl2, Bl3; Compare1 cp0(A4[0], B4[0], e0, Al0, Bl0); Compare1 cp1(A4[1], B4[1], e1, Al1, Bl1); Compare1 cp2(A4[2], B4[2], e2, Al2, Bl2); Compare1 cp3(A4[3], B4[3], e3, Al3, Bl3); assign Equal = (e0 & e1 & e2 & e3); assign Alarger = (Al3 | (Al2 & e3) | (Al1 & e3 & e2) | (Al0 & e3 & e2 & e1)); assign Blarger = (~Alarger & ~Equal); endmodule Winter ZDMC – Lec. #1 – 20

21 Final thoughts Verilog looks like C, but it describes hardware
EE141 Final thoughts Verilog looks like C, but it describes hardware Multiple physical elements, Parallel activities Temporal relationships Basis for simulation and synthesis Figure out the circuit you want, then figure out how to express it in Verilog Understand the elements of the language Modules, ports, wires, reg, primitive, continuous assignment, blocking statements, sensitivity lists, hierarchy Best done through experience Behavioral constructs hide a lot of the circuit details but you as the designer must still manage the structure, data-communication, parallelism, and timing of your design. Winter ZDMC – Lec. #1 – 21

22 HDL MODELS OF COMBINATIONAL CIRCUITS
组合逻辑电路的硬件描述 HDL MODELS OF COMBINATIONAL CIRCUITS 22 Winter ZDMC – Lec. #1 – 22

23 可综合的组合逻辑电路设计 组合逻辑电路简介 任何时刻电路的输出仅与该时刻的输入有关的数字电路被称为组合逻辑电路。
组合电路不含有反馈，不含有记忆元件，仅仅通过若干门电路连接实现的。 组合逻辑的表达一般有3种方式：真值表、逻辑表达式和电路原理图。 Winter ZDMC – Lec. #1 – 23

24 可综合的组合逻辑电路设计 使用Verilog HDL描述组合电路有多种方式 (1) 与真值表对应地是用户自定义原语。
(2) 与电路图对应地是门级建模即结构描述 (3) 与逻辑表达式对应地称为行为描述。 Winter ZDMC – Lec. #1 – 24

25 可综合的组合逻辑电路设计 用Verilog语言可以有多种方式描述组合电路，但是有些综合工具 并不支持每一种描述方式。大多数综合工具可综合下面三种形式描述的组合电路。 （1）门级模型 门级模型是描述逻辑门以及逻辑门之间连接关系的模型，通过门原语描述电路。 Winter ZDMC – Lec. #1 – 25

26 可综合的组合逻辑电路设计 Verilog HDL中提供了丰富的门类型关键字，用于电路的门级描述。Verilog HDL有关类型的关键字共有26个，比较常用的有下面几个： not 非门 nor 或非门 and 与门 xor 异或门 nand 与非门 xnor 异或非门 or 或门 buf 缓冲器 Winter ZDMC – Lec. #1 – 26

27 可综合的组合逻辑电路设计 调用门原语的句法如下： 门类型关键字 实例化的门名称(端口列表) 端口列表按下列顺序列出：
门类型关键字 实例化的门名称(端口列表) 端口列表按下列顺序列出： (输出，输入1，输入2，输入3 ， ……)； 对于三态门，则按如下顺序列出端口 (输出，输入，使能控制端)； 比如： and myand(out,in1,in2,in3)；//三输入与门 and amd1(out,in1,in2)； //二输入与门 buffif1 mytri(out,in,enable)； //高电平使能的三态门 Winter ZDMC – Lec. #1 – 27

28 可综合的组合逻辑电路设计 例1 2-4译码器 Module decoder(D,A,B,enable) Output [ 0:3] D;
input A,B; Input enable; wire A_not,B_not,enable_not; not G1(A_not,A) ， G2(B_not,B), G3(enable_not) nand G4(D[0], A_not, B_not, enable_not) , G5(D[1], A_not, B, enable_not) , G6(D[2], A, B_not, enable_not) , G7(D[3], A, B, enable_not) , endmodule Winter ZDMC – Lec. #1 – 28

29 可综合的组合逻辑电路设计 （2）数据流模型 利用连续赋值语句assign来描述一个组合电路。综合器可以把用连续赋值描述的电路翻译成布尔等式并优化。它对操作数进行不同的操作以得到需要的结果，提供了30多种对操作数的操作，下面列出了常见的几种： Winter ZDMC – Lec. #1 – 29

30 可综合的组合逻辑电路设计 symbol operation + binary addition – binary subtraction
& bitwise AND ^ bitwise XOR ︱ bitwise OR ～ bitwise not == equality > greater than < less than { } concatenation ? : conditional Winter ZDMC – Lec. #1 – 30

31 可综合的组合逻辑电路设计 例2 4bit加法器 module adder4(cout,sum,ina,inb,cin);
output[3:0] sum; output cout; input[3:0] ina,inb; input cin; assign {cout,sum} = ina+inb+cin; endmodule Winter ZDMC – Lec. #1 – 31

32 可综合的组合逻辑电路设计 例3 4bit比较器器 module mag_compare
( output A_it_B,A_eq_B,A_gt_B, input[3:0] A,B ); assign A_it_B=(A<B); assign A_gt_B=(A>B); assign A_eq_B=(A=B); endmodule Winter ZDMC – Lec. #1 – 32

33 可综合的组合逻辑电路设计 （3）行为级模型 行为级模型通常用来描述时序逻辑电路，但有时候也可以用来描述组合逻辑电路。
行为级模型使用关键词always来进行描述，其声明格式如下： always <时序控制 or 事件控制> <语句> always语句在仿真过程中是不断活动的。但always语句后面跟着的过程快是否执行，则要看它的触发条件是否满足，如满足则运行过程快一次；不满足，则不断的循环执行。 Winter ZDMC – Lec. #1 – 33

34 可综合的组合逻辑电路设计 例4 2-1选择器 module mux(m_out,A,B,select); output m_out;
例4 2-1选择器 module mux(m_out,A,B,select); output m_out; input A,B,select; reg m_out; or B or select); if (select==1) m_out=A; else m_out=B; endmodule 当信号A，B，select中的任何一个发生变化时，将会触发下面语句执行 Winter ZDMC – Lec. #1 – 34

35 可综合的组合逻辑电路设计 例5 4-1选择器 module mux ( output reg m_out,
例5 4-1选择器 module mux ( output reg m_out, input in_0,in_1,in_2,in_3, input[1:0] select); select) case(select) 2’b00: m_out=in_0; 2’b01: m_out=in_1; 2’b10: m_out=in_2; 2’b11: m_out=in_3; endcase endmodule Winter ZDMC – Lec. #1 – 35

36 可综合的组合逻辑电路设计 Test Bench
编写test bench 的目的是验证设计的正确性。通过模拟各种可能的情况查看输入输结果是否符合设计的要求。简单的test bench要向设计提供向量，人工验证输出。 除了使用always语句外，它还使用initial来产生激励給被测试的模块。 Winter ZDMC – Lec. #1 – 36

37 可综合的组合逻辑电路设计 initial 模块如下： initial begin A = 0;B=0; #10 A=1;
end 在这个例子中用initial语句在仿真开始时对变量A，B进行初始化，这个初始化的过程不需要任何仿真时间，在10ns之后，变量A变1,20ns之后变量A为0，B为1。 Winter ZDMC – Lec. #1 – 37

38 可综合的组合逻辑电路设计 Verilog中常用的系统任务
$display(p1,p2,…,pn);将参数p2到pn按p1给定的格式输出,自动的在输出后换行 $write（p1p2 ,…,pn ；与$display相同，只是在输出后不换行 $monitor 提供了监视和输出参数列表中的表达式或变量值的功能 $time 返回一个64位的整数来表示当前仿真时刻 $finish 退出仿真 Winter ZDMC – Lec. #1 – 38

39 可综合的组合逻辑电路设计 激励模块的格式通常如下所示： Module test_module_name
//Declare local reg and wire identifiers（标识符）. //Instantiate(实例化) the design module under test. //Specify a stopwatch,using $finish to terminate the simulation. //Generate stimulus ,using initial and always statements //Display the output response endmodule Winter ZDMC – Lec. #1 – 39

40 可综合的组合逻辑电路设计 例 6 2-1选择器的test bench module mux; wire t_mux_out;
reg t_A,t_B; reg t_select; parameter stop_time=50; mux M1(t_mux_out, t_A,t_B, t_select); initial # stop_time $finish; initial begin t_select=1;t_A=0;t_B=1; #10 t_A=1;t_B=0; Winter ZDMC – Lec. #1 – 40

41 可综合的组合逻辑电路设计 #10 t_select=0; #10 t_A=0;t_B=1; end initial begin
$monitor(“time=“”,$time, “select=%b A=%b B=%b OUT=%b, t_select, t_A,t_B, t_mux_out); endmodule Winter ZDMC – Lec. #1 – 41