Positive gate bias-Induced Reliability in IGZO TFT

Presentation on theme: "Positive gate bias-Induced Reliability in IGZO TFT"— Presentation transcript:

1 Positive gate bias-Induced Reliability in IGZO TFT
Ling Wang

2 Outline Existing explanation
Charge trap/detrap in oxide(CdSe/a-Si TFT) Problem and possible solution

3 Existing explanation (a) Charge trap in oxide (b) Donor trap creation
VZn2- ;large Zn atom, difficult to recovery (c) Charge trap in bulk [1]: more electrons are trapped in the bulk during the stress; charge centroids move towards the back surface-negative VBS-positive Vth shift（substrate bias effect） [1] Ken Hoshino,TED,2009

4 Existing explanation Charge trap in bulk Ec EF Ev
加应力，体区trapped的电子会增多，但是这些电子在撤去应力后会很快释放掉，不会产生影响。主要起作用的是channel中的被deep state trap的 electrons，引起Vth 左漂。 实际器件中Recovery需要的时间比较长，因而机理主要是charge trapped in oxide [2] C. van Berkel, JAP,1989

5 Charge trap/detrap in oxide
Tunneling into the oxide captured by trap-SRH Tunnel的条件： 足够大的隧穿几率（势垒足够薄） 一侧有电子，另一侧在相同能量的地方有空能级 [3] KOELMANS and H. C. DE GRAAFF, SSE,1967

6 Charge trap/detrap in oxide
[4] Arash A. Fomani and Arokia Nathan,JAP,2011

7 Discussion Results X0=60A, Xoc=100A, 在隧穿的范围内 Problems 没有体现电场和温度的影响

8 Possible solution 电场的作用 温度的作用 a Oxide中连续分布的trap-高电场下较高能级的 trap能参与
加速电子在trap之间的跳跃，为tunnel提供空能级 EF 100A Ec Ev ET