醫工所碩士二年級 R 葉昱甫 電子所碩士一年級 R 謝博鈞 電信所碩士一年級 R 王欣平

Presentation on theme: "醫工所碩士二年級 R 葉昱甫 電子所碩士一年級 R 謝博鈞 電信所碩士一年級 R 王欣平"— Presentation transcript:

1 醫工所碩士二年級 R90548009 葉昱甫 電子所碩士一年級 R91943057 謝博鈞 電信所碩士一年級 R91942041 王欣平
Group 6 醫工所碩士二年級 R 葉昱甫 電子所碩士一年級 R 謝博鈞 電信所碩士一年級 R 王欣平

2 Outline HW/SW Partition Design Hardware Design Simulation Model

3

4 Accumulative Multiplication
Suitable for Hardware Processing

5 Also suitable for Hardware

6 Quantization It is basically a set of division operations and a simple table lookup. Suitable for Hardware

7 Zigzag scan Huffman Coding Reordering of sequence Not suitable for HW
Pure table lookup Suitable for Software

8 Design Block Diagram Hardware RGB to YUV 8x8 Blocks DCT Quantization
Compressed Image Huffman Coding Zigzag Scan Software

9

10 Timing diagram

11 MYIP

12 Syntax 1.Check error Top Module Sub module 1 Make File Sub module 2
2.Auto make hierarchy for design Top Module Sub module 1 Make File Sub module 2 Net.v Xilinx Sub module 4 Sub module3 design script

13 Simulation environment
Environment TOP Sub module 1 Sub module 2 Sub module3 Sub module 4 design ARM AHBA Test pattern model

14 Net.v

15 Conclusion After knowing the algorithms, we try to make a good HW/SW Partition We design the block diagram of Hardware We try to make a Simulation Model, which can guarantee the Hardware can work