邏輯閘 Logic Gates Chapter 3

邏輯基本含意 是指人類的推理範疇, 告訴我們如果某些條件為真時, 某一個命題(陳述式)就是真的. 例如: 如果 “燈泡沒有燒毀” 是真並且 “開關打開” 也是真, 則命題 “燈是亮的” 是真. 因此這個邏輯敘述可以說成:只有燈泡沒燒毀而且開關打開時燈才是亮的. 以邏輯運算來看, 這些真/假或是/否的陳述可用具有0與1兩種狀態之數位電路來實現

正邏輯與負邏輯

正邏輯與負邏輯

3-1倒相(反相)器的符號 The Inverter Figure 3--1 Standard logic symbols for the inverter (ANSI/IEEE Std. 91-1984). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

負性與極性標記 負性標記(negation indicator) 極性標記(polarity indicator) 當其在輸入端，表示0為引發電路動作的輸入稱之為LOW- 動作輸入方式. 極性標記(polarity indicator) 是指圖3-1( b)以三角形表示。 當其在輸入端，表示LOW位準 是引發電路動作的輸入狀態.

倒相(反相)器的真值表 Inverter truth table Input Output Low (0) High (1) High (1) Low (0) Boolean Equation Output = Input X = A

倒相器的時序圖 Inverter Timing diagram Figure 3--3 Timing diagram for the case in Figure 3-2.

Figure 3--6 The inverter complements an input variable. 反相器的邏輯運算式與應用 將輸入 變數反向 Figure 3--6 The inverter complements an input variable. 用反向器 產生1的 補數 Figure 3--7 Example of a 1’s complement circuit using inverters. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

3-2 及閘的符號 The AND gate Figure 3--8 Standard logic symbols for the AND gate showing two inputs (ANSI/IEEE Std. 91-1984). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

及閘的真值表 AND gate truth table A B Output Low (0) Low (0) Low (0) Low (0) High (1) Low (0) High (1) Low (0) Low (0) High (1) High (1) High (1) Boolean Equation X = AB

及閘的輸入與輸出之關係 Figure 3--9 All possible logic levels for a 2-input AND gate. Open file F03-09 to verify AND gate operation. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

脈波輸入的操作結果 Figure 3--10 Example of pulsed AND gate operation with a timing diagram showing input and output relationships. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-3 如果將圖3-11中A、B波形輸入AND閘則產生的輸出波形為何 ? Figure 3--11 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-4 針對圖 3-12 中輸入波形A、B，畫出對應於輸入的正確輸出波形? Figure 3--12 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-5 考慮圖3-13的三輸入波形，試畫出相對輸入的輸出波形。 例題 3-5 考慮圖3-13的三輸入波形，試畫出相對輸入的輸出波形。 Figure 3--13 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

兩個,三個,四個輸入端的AND閘之布林表示式 Figure 3--14 Boolean expressions for AND gates with two, three, and four inputs. 兩個,三個,四個輸入端的AND閘之布林表示式 Figure 3--15 An AND gate performing an enable/inhibit function for a frequency counter. 用AND閘啟動抑制頻率計數器執行自身的功能 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--16 A simple seat belt alarm circuit using an AND gate. 點火開關On的時候為High, Off的時候為Low. 警報器 安全帶沒扣的時候為High, 扣好的時候為Low. 定時器延遲30秒 Figure 3--16 A simple seat belt alarm circuit using an AND gate. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

3-3 或閘的邏輯符號 The OR gate Figure 3--17 Standard logic symbols for the OR gate showing two inputs (ANSI/IEEE Std. 91-1984). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

或閘的真值表 OR gate truth table A B Output Low (0) Low (0) Low (0) Low (0) High (1) High (1) High (1) Low (0) High (1) High (1) High (1) High (1) Boolean Equation X = A+B

或閘的輸入與輸出之關係 Figure 3--18 All possible logic levels for a 2-input OR gate. Open file F03-18 to verify OR gate operation. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

脈波輸入的操作情形 Figure 3--19 Example of pulsed OR gate operation with a timing diagram showing input and output time relationships. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-6 如果將圖 3-20 中的A、B 兩個波形輸入OR閘，則其輸出波形為何。? Figure 3--20 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-7在圖 3-21 中輸入波形A、B ， 試畫出與輸入波形具有正確時間對應關係的輸出波形。 Figure 3--21 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-8考慮圖3-22的三輸入OR閘和輸入波形，試畫出在時間軸上正確對應於輸入波形的輸出波形。 Figure 3--22 OR 閘的邏輯數學式 Figure 3--23 Boolean expressions for OR gates with two, three, and four inputs. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--24 A simplified intrusion detection system using an OR gate. 門窗開啟感應器(磁簧開關) 開啟時為High, 關閉時為Low. Figure 3--24 A simplified intrusion detection system using an OR gate. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

3-4 反及閘的邏輯符號 The NAND gate Figure 3--25 Standard NAND gate logic symbols (ANSI/IEEE Std. 91-1984). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

反及閘的真值表 NAND gate truth table A B Output Low (0) Low (0) High (1) Low (0) High (1) High (1) High (1) Low (0) High (1) High (1) High (1) Low (0) Boolean Equation X = AB

例題 3-9 Figure 3--27 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-10 Figure 3--28 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

NAND閘與負OR 閘擁有等效的操作情形 A B Output Low (0) Low (0) High (1) Figure 3--29 Standard symbols representing the two equivalent operations of a NAND gate. A B Output Low (0) Low (0) High (1) Low (0) High (1) High (1) High (1) Low (0) High (1) High (1) High (1) Low (0) 只要有一個 0 全部都是 1 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

當兩個桶子的水都 超過1/4時綠燈亮, 只要有任一桶的水 未達到1/4則綠燈 滅掉. 例題 3-11 監測製造工廠兩個儲存槽液面高度，使用NAND閘完成此邏輯功能。 水位感應器 A桶 B桶 當兩個桶子的水都 超過1/4時綠燈亮, 只要有任一桶的水 未達到1/4則綠燈 滅掉. 水位感應器 Figure 3--30 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

當兩個桶子的水, 只要 有任一桶或兩桶的水不 到1/4 時紅燈亮, 兩桶 的水都超過1/4則紅燈 滅掉. 例題 3-12監測製造工廠兩個儲存槽液面高度，使用負 OR閘完成此邏輯功能。 當兩個桶子的水, 只要 有任一桶或兩桶的水不 到1/4 時紅燈亮, 兩桶 的水都超過1/4則紅燈 滅掉. Figure 3--31 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

圓圈表示「邏輯0」才動作 可視為加NOT運算 例題 3-13 Figure 3--32 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--33 Standard NOR gate logic symbols (ANSI/IEEE Std. 91-1984). 3-5 反或閘的邏輯符號 The NOR gate Figure 3--33 Standard NOR gate logic symbols (ANSI/IEEE Std. 91-1984). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

反或閘的真值表 NOR gate truth table A B Output Low (0) Low (0) High (1) Low (0) High (1) Low (0) High (1) Low (0) Low (0) High (1) High (1) Low (0) Boolean Equation X = A+B

例題 3-14 Figure 3--35 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-15 Figure 3--36 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

NOR閘與負AND 閘擁有等效的操作情形 A B Output Low (0) Low (0) High (1) Figure 3--37 Standard symbols representing the two equivalent operations of a NOR gate. A B Output Low (0) Low (0) High (1) Low (0) High (1) Low (0) High (1) Low (0) Low (0) High (1) High (1) Low (0) 全部都是0 只要有一個1 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

著陸前, 3組機輪中,只要 有任一組以上的機輪未順 利伸展, 則紅燈亮. 起落架感應器 機輪伸展時輸出0, 機輪收回時輸出1. 例題 3-17 航空器功能監視系統 起落架感應器 機輪伸展時輸出0, 機輪收回時輸出1. 著陸前, 若3組機輪全部 順利伸展, 則綠燈亮. Figure 3--39 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-18 Figure 3--40 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--41 Standard logic symbols for the exclusive-OR gate. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

排斥或閘的真值表 Exclusive-OR gate truth table A B Output Low (0) Low (0) Low (0) Low (0) High (1) High (1) High (1) Low (0) High (1) High (1) High (1) Low (0) Boolean Equation X = AB+BA = AB Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--44 Standard logic symbols for the exclusive-NOR gate. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

反排斥或閘的真值表 Exclusive-NOR gate truth table A B Output Low (0) Low (0) High (1) Low (0) High (1) Low (0) High (1) Low (0) Low (0) High (1) High (1) High (1) Boolean Equation X = A B + B A = AB Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--46 Example of pulsed exclusive-OR gate operation. 脈波輸入的操作情形 Figure 3--46 Example of pulsed exclusive-OR gate operation. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-20 Figure 3--47 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--48 An XOR gate used to add two bits. (XOR當作加法器) 應用範例:加法器 Figure 3--48 An XOR gate used to add two bits. (XOR當作加法器) Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

3-7 固定功能邏輯元件:IC邏輯閘 CMOS series ICs 5 Volt category 74HC and 74HCT High-speed CMOS 74AC and 74ACT Advanced CMOS 74AHC and 74AHCT Advanced High-speed CMOS 3.3 volt category 74LV Low-voltage CMOS 74LVC Low-voltage CMOS 74 ALVC Advanced Low-voltage CMOS

CMOS series ICs Continued 4000 series CMOS BiCMOS 結合 TTL 和 CMOS 74BCT BiCMOS 74ABT Advanced BiCMOS 74LVT Low-voltage BiCMOS 74ALB Advanced Low-Voltage BiCMOS

TTL series logic gates 74 standard TTL (no letter) 74S Schottky TTL 74AS Advanced Schottky TTL 74LS Low-power Schottky TTL 74ALS Advanced Low-power Schottky TTL 74F Fast TTL

IC 封裝 Figure 3--49 Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

IC 封裝 Figure 3--50 Pin configuration diagrams for some common fixed-function IC gate configurations. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

邏輯符號 Figure 3--51 Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in any CMOS or TTL series. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

效率, 特性和參數 Performance Characteristics and Parameters Propagation delay Time (傳輸延遲時間) DC Supply Voltage (VCC) (直流電源) Power Dissipation (功率消耗) Input and Output Logic Levels (輸入輸出邏輯位準) Speed-Power product (速度-功率的乘積) Fan-Out and Loading (扇出和負載能力)

Figure 3--52 傳遞延遲時間 (propagation delay times ) 效能特性與參數 傳遞延遲時間 例題 3-21 Figure 3--52 傳遞延遲時間 (propagation delay times ) Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

效能特性與參數 功率消耗

效能特性與參數 功率消耗 功率消耗PD值等於直流電壓源與平均供應電流值的乘積

效能特性與參數 輸入輸出邏輯準位

效能特性與參數 輸入輸出邏輯準位

效能特性與參數 輸入輸出邏輯準位

效能特性與參數 輸入輸出邏輯準位

效能特性與參數 輸入輸出邏輯準位

效能特性與參數 SPP = tpPD 速度功率乘積 速度功率乘積(SPP)是評量邏輯電路效能另一項參數, 越小越好 例題 3-22 某個邏輯閘 tp=5ns, ICCH=1ma, 且ICCL=2.5ma, VCC=5V, 求其SPP值 PD=VCC[(ICCH+ICCL)/2]=5[(1ma+2.5ma)/2]=8.75mw SPP=tpPD=(5ns)(8,75mw)=43.75pJ

扇出與負載 Fanout扇出能力: 1個LS的邏輯閘, 可以推20個LS的 邏輯閘. 推動閘 負載閘 Figure 3--53 The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

CMOS與TTL效能比較 (傳遞延遲時間) (功率消耗) Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

CMOS與TTL效能比較 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--55 The partial data sheet for a 74HC00A. 特性資料表 Figure 3--55 The partial data sheet for a 74HC00A. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--56 The effect of an open input on a NAND gate. IC邏輯閘的內部錯誤 從開路端加入脈波時, 輸出端不會有脈波. 從正常端加入脈波時, 輸出端會有脈波, 因為 開路端在TTL被視為加 邏輯1. Figure 3--56 The effect of an open input on a NAND gate. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

輸入端開路的故障檢修 Figure 3--57 Troubleshooting a NAND gate for an open input with a logic pulser and probe. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

輸出端內部開路的故障檢修 Figure 3--58 Troubleshooting a NOR gate for an open output with a logic pulser and probe. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-23 我們檢查一顆74LS10 IC（如圖），我們已用邏輯探針檢查第一、二接腳處於High狀態。如圖所示之探針反應說明可能故障原因。 Figure 3--59 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-24 操作圖3-60 頻率計數器，不管輸入信號為何，顯示器輸出一直為0。試判斷造成此功能失常的原因。 Figure 3--60 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

例題 3-25 圖 3-61的頻率計數器所量測的輸入信號頻率是錯誤的試判斷引起錯誤可能原因。 Figure 3--60 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Troubleshooting Which gates are not functionally correctly?

Answer The AND and NOR were faulted

Figure 3--62 An example of a basic programmable OR array. 可程式化邏輯：基本觀念 可程式化陣列 – OR閘陣列 Figure 3--62 An example of a basic programmable OR array. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--63 An example of a basic programmable AND array. 可程式化邏輯：基本觀念 可程式化陣列 – AND 閘陣列 Figure 3--63 An example of a basic programmable AND array. Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--67 Block diagram of a PROM (programmable read-only memory). SPLD分類 – 可程式化唯讀記憶體 Figure 3--67 Block diagram of a PROM (programmable read-only memory). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--64 Block diagram of a PROM (programmable read-only memory). SPLD分類 – 可程式化唯讀記憶體 A7(I4,I3,I2,I1,I0)=(0,2,3,….,29) Figure 3--64 Block diagram of a PROM (programmable read-only memory). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--68 Block diagram of a PLA (programmable logic array). SPLD分類 – 可程式化邏輯陣列(PLA) Figure 3--68 Block diagram of a PLA (programmable logic array). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

SPLD分類 – 可程式化邏輯陣列(PLA) F1=AB’+AC+A’BC’ F2=(AC+BC)’ Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--69 Block diagram of a PAL (programmable array logic). SPLD分類 – 可程式化陣列邏輯(PAL) Figure 3--69 Block diagram of a PAL (programmable array logic). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

SPLD分類 – 可程式化陣列邏輯(PAL) W=ABC’+A’B’CD’ Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 3--67 Block diagram of a GAL (generic array logic). SPLD分類 – 泛型陣列邏輯(GAL) Figure 3--67 Block diagram of a GAL (generic array logic). Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

VHDL 介紹

Entity all inputs and outputs 的描述 每一 VHDL 設計必須至少有一個以上 entity 宣告entity時需用識別字（identifiers）。命名entity本身以及input、output信號 Entity 是一關鍵字

識別字(Identifiers) 使用者自行定義，以便區別VHDL元素與單元名稱。 Two types of identifiers Basic identifiers Extended identifiers

VHDL基本識別字規則 基本識別字只能由小寫或大寫字母, 數字及單一底線組成。 識別字名稱第一個符號必須是字母。 基本識別字不能含有空白字元。 VHDL關鍵字或保留字不能作為識別字。 附錄 D是VHDL的關鍵字及保留字列表 例如：A、B1、X、MyAND、ORgate、Decoder_I2。

Entity declaration entity <entity identifier> is port (signal identifier); end entity <entity identifier> entity OR_1 is port (A,B: in bit; X: out bit); end entity OR_1

Port 敘述式 port 代表 input或output signal port 是一 VHDL 關鍵字 port敘述式必須指明其port識別字、port的方向(輸入或輸出)與port的資料型別(data type) 。 port的3種方向in, out, inout 。 Bit是VHDL許多不同的資料型別其中一種。 bit 其值只允許0或1。

二輸入OR的port敘述式 port (A, B: in bit; X: out bit); 兩個輸入port為A與B 一個輸出port為X Prot敘述式結束符號; Port的方向是in 或 out Bit 是資料型別

架構(Architecture) architecture宣告是放置實體（Entity）邏輯功能的操作過程 每一實體(entity)都必須有一個相對應的architecture 每一architecture必須指出與其相關的實體(entity)名稱

architecture < architecture name> of <entity name> is begin The description of the logic function goes here end architecture <architecture name architecture ORfunction of OR_1 is begin X <= A or B; end architecture ORfunction;

Program for 2-input OR gate entity OR_1 is port (A,B: in bit; X: out bit); end entity OR_1 architecture ORfunction of OR_1 is Begin X <= A or B; end architecture ORfunction;

Programming VHDL 註解符號是- - 資料流描述法(Data flow descriptions) X <= A 資料從輸入流到輸出的過程。 行為描述法(Behavioral description 被使用在邏輯功能太複雜的情況 它根據特定時間下的函數與輸入狀態來描述邏輯的操作 X <=‘1’ when (A=‘0’) else ‘0’

邏輯運算子 運算子 說明 and 只有在所有輸入信號為1時，才回傳0 or 當任何輸入信號為1時，就回傳1 not 如果輸入信號為0，則回傳1；如果輸入為1，則回傳0 nand 當任何輸入信號為0時，就回傳1 nor 當所有輸入信號為0時，則回傳1 xor 當只有一個輸入信號為1時，回傳1 xnor 當兩個輸入信號同時為1或0時，回傳1

Program for 3-input AND gate entity AND_gate is port (A, B, C,: in bit; X: out bit); end entity AND_gate; architecture ANDfunction of AND_gate is Begin X <= A and B and C; end architecture ANDfunction

本章摘要 Figure 3--72 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

習題 3-25 請根據圖3-87的示波器顯示波形，判斷 tPLH與tPHL的值。兩個通道上的刻度單位均為V /div sec /div。 Figure 3--87 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

習題 3-49 請設計一組能適用於圖3-97中米黃色方塊的電路，這個電路使汽車在啟動開關關閉後，於車大燈開關仍然開啟的條件下，會持續電亮15秒後才自動熄滅。假設使車大燈熄滅所需的信號是LOW狀態。 點火開關 車大燈開關 兩個輸入端都輸入1, 輸出端才輸出1. Figure 3--97 Thomas L. Floyd Digital Fundamentals, 8e Copyright ©2003 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

End of Chapter 3