缓存 缓存 Cache 1、缓存概述 2、缓存使用 3、缓存一致性问题

内存架构 减少内存平均访问时间

缓存原理 y[0] = h[0] × x[0] + h[1] × x[1] + ... + h[5] × x[5] Cache Line

C674x Cache Memory 架构

C674x Cache Memory 架构 缓存 描述 替换策略 可缓存性 访问时间 大小 Cache Line L1 Program 程序 直接映射（Direct Mapped） 读分配（Read Allocate） 总是缓存 1 Cycle 4K / 8K / 16K / 32K 字节 32 字节 L1 Data 数据 2 路组相关（Set Associative） 回写（Write Back） 最近最少使用（Least Recently Used (LRU)） 可配置 64 字节 L2 程序及数据 4 路组相关（Set Associative） 读写分配（Read & Write Allocate） 32K / 64K / 128K / 256K 字节 Allocation The process of finding a location in the cache to store newly cached data. This process can include evicting data that is presently in the cache to make room for the new data. Direct-mapped cache A direct-mapped cache maps each address in the lower-level memory to a single location in the cache. Multiple locations may map to the same location in the cache. This is in contrast to a multi-way set-associative cache, which selects a place for the data from a set of locations in the cache. A direct-mapped cache can be considered a single-way set-associative cache. Read allocate A read-allocate cache only allocates space in the cache on a read miss. A write miss does not cause an allocation to occur unless the cache is also a write-allocate cache. For caches that do not write allocate, the write data would be passed on to the next lower-level cache.

L1 Program Cache Memory 架构 16KBytes Line A cache line is the smallest block of data that the cache operates on. The cache line is typically much larger than the size of data accesses from the CPU or the next higher level of memory. For instance, although the CPU may request single bytes from memory, on a read miss the cache reads an entire line's worth of data to satisfy the request. Dirty In a writeback cache, writes that reach a given level in the memory hierarchy may update that level, but not the levels below it. Therefore, when a cache line is valid and contains updates that have not been sent to the next lower level, that line is said to be dirty. The opposite state for a dirty cache line is clean. Line frame A location in a cache that holds cached data (one line), an associated tag address, and status information for the line. The status information can include whether the line is valid, dirty, and the current state of that line's LRU. Valid When a cache line holds data that has been fetched from the next level memory, that line frame is valid. The invalid state occurs when the line frame holds no data, either because nothing has been cached yet, or because previously cached data has been invalidated for whatever reason (coherence protocol, program request, etc.). The valid state makes no implications as to whether the data has been modified since it was fetched from the lower-level memory; rather, this is indicated by the dirty or clean state of the line. Miss A cache miss occurs when the data for a requested memory location is not in the cache. A miss may stall the requestor while the line frame is allocated and data is fetched from the next lower level of memory. In some cases, such as a CPU write miss from L1D, it is not strictly necessary to stall the CPU. Cache misses are often divided into three categories: compulsory misses, conflict misses, and capacity misses.

L1 Data Cache Memory 架构 16KBytes Line A cache line is the smallest block of data that the cache operates on. The cache line is typically much larger than the size of data accesses from the CPU or the next higher level of memory. For instance, although the CPU may request single bytes from memory, on a read miss the cache reads an entire line's worth of data to satisfy the request. Dirty In a writeback cache, writes that reach a given level in the memory hierarchy may update that level, but not the levels below it. Therefore, when a cache line is valid and contains updates that have not been sent to the next lower level, that line is said to be dirty. The opposite state for a dirty cache line is clean. Line frame A location in a cache that holds cached data (one line), an associated tag address, and status information for the line. The status information can include whether the line is valid, dirty, and the current state of that line's LRU. Valid When a cache line holds data that has been fetched from the next level memory, that line frame is valid. The invalid state occurs when the line frame holds no data, either because nothing has been cached yet, or because previously cached data has been invalidated for whatever reason (coherence protocol, program request, etc.). The valid state makes no implications as to whether the data has been modified since it was fetched from the lower-level memory; rather, this is indicated by the dirty or clean state of the line. Miss A cache miss occurs when the data for a requested memory location is not in the cache. A miss may stall the requestor while the line frame is allocated and data is fetched from the next lower level of memory. In some cases, such as a CPU write miss from L1D, it is not strictly necessary to stall the CPU. Cache misses are often divided into three categories: compulsory misses, conflict misses, and capacity misses.

使用缓存 缓存大小 L1 Program L1 Data L2 可缓存性 配置 MAR

StarterWare SYS/BIOS 缓存大小配置 #include "dspcache.h" CacheEnable(L1DCFG_L1DMODE_32K | L1PCFG_L1PMODE_32K | L2CFG_L2MODE_256K); SYS/BIOS #include <ti/sysbios/family/c64p/Cache.h> Cache_Size cacheSize; cacheSize.l1pSize = Cache_L1Size_32K; cacheSize.l1dSize = Cache_L1Size_32K; cacheSize.l2Size = Cache_L2Size_256K; Cache_setSize(&cacheSize); 缓存大小配置

StarterWare SYS/BIOS 内存可缓存性配置 #include "dspcache.h" CacheEnableMAR((unsigned int)0xC0000000, (unsigned int)0x08000000); SYS/BIOS #include <ti/sysbios/family/c64p/Cache.h> Cache_setMar((Ptr *)0x80000000, 0x10000000, Cache_Mar_ENABLE; 内存可缓存性配置

内存可缓存性配置

内存可缓存性配置 TMS320C674x DSP Megamodule Reference Guide

缓存架构

缓存访问流程

缓存一致性问题 读取数据 / 写入数据 其它 主外设 缓存 内存 CPU 核心 在任何时刻，CPU 或者其它 Master 访问存储器中数据时，由于CACHE 的存在造成不 能够得到最近更新过的数据，就会出现CACHE 一致性问题。

缓存一致性问题 类型 L1 Program L1 Data L2 DDR 程序 不需要缓存 不存在一致性问题 N/A 存在一致性问题 1、程序被 CPU 修改 2、程序被主外设修改 软件维护一致性 数据 硬件维护一致性

硬件维护缓存一致性 L2 数据被其它主外设更新时 L2 控制器会根据地址检测数据是否存在于 L1 Data 如果在硬件就从 L2 复制到 L1 Data CPU 读取数据时 如果在 L1 Data 就读取 如果不在就直接从 L2 读取 L2 数据被 CPU 更新时 其它主外设读取数据时 L2 控制器会根据地址检测数据是否存在于 L1 Data 如果在硬件就直接从 L1 Data 读取 如果不在就从 L2 读取

软件维护缓存一致性 缓存一致性维护操作 Cache 数据失效 Cache 数据回写 Cache 数据失效并回写 操作 L1 Program L1 Data L2 全局失效 L1PINV L1DINV L1INV 全局回写 N/A L1DWB L2WB 全局失效并回写 L1DWBINV L2WBINV 部分失效 L1PIBAR / L1PIWC L1DIBAR / L1DIWC L2IBAR / L2IWC 部分回写 L1DWBAR / L1DWWC L2WBAR / L2WWC 部分失效并回写 L1DWIBAR / L1DWIWC L2WIBAR / L2WIWC

软件维护缓存一致性 - 程序 缓存一致性维护操作 CPU 核心对代码的修改怎么办？ Cache 数据失效 Cache 数据回写 其它主外设对 L2 中代码修改 其它主外设对 DDR 中代码修改 L1P 读分配

软件维护缓存一致性 - 数据 缓存一致性维护操作 CPU 核心对代码的修改怎么办？ Cache 数据失效 Cache 数据回写 CPU 对 DDR 读操作 CPU 对 DDR 写操作 L1P 读分配

StarterWare SYS/BIOS 软件维护缓存一致性 #include "dspcache.h" CacheInvL1pAll(); CacheInv(unsigned int baseAddr, unsigned int byteSize); CacheWBAll(); CacheWB(unsigned int baseAddr, unsigned int byteSize); CacheWBInvAll(); CacheWBInv(unsigned int baseAddr, unsigned int byteSize); SYS/BIOS #include <ti/sysbios/family/c64p/Cache.h> Cache_inv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait); Cache_invL1pAll(); Cache_wb(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait); Cache_wbAll(); Cache_wbInv(Ptr blockPtr, SizeT byteCnt, Bits16 type, Bool wait); Cache_wbInvAll(); 软件维护缓存一致性