JTAG INTERFACE SRAM TESTER WITH C-LCM Reporter: Team One

Our Project Name JTAG Jo Tone-co Ai Group >o<

Working distribution SRAM [johnny751125] Tester [kcir] Coding Document hcsoso、jackson59、Sinze Tester [kcir] Coding mimi9126、troychang、JAST、 gomibako、reeetingay Document swallow0130、asurada0207

Introduction to JTAG

What’s JTAG? Interface 可用來偵測晶片(chip)的缺陷以及是否運作正常

Common memory problems Memory chip catastrophic failure Circuit board the wiring between the processor and memory device missing memory chips improperly inserted memory chips

Electrical wiring problems address line：儲存到錯誤位址 data line：data不正確 control line：可能導致data根本沒有存入

Missing memory chips 記憶體那個位置上面根本就沒有晶片

Improperly inserted chips 記憶體上某個component的位置放錯所造成

The order of executing tests data bus test address bus test device test

Data bus test 測試目標 確認processor放在bus上 的值和memory device端 讀到的是同一個值 測試方式 Walking 1’s bit 00000001 00000010 00000100 00001000 00010000 00100000 01000000 10000000

只需要測試2的次方數(power-of-2)的那些位址 Address Bus test Naive 針對每一個cell做測試 Faster 針對每個address bus的 pin腳做測試 00000001 01h 00000010 02h 00000100 04h 00001000 08h 00010000 10h 00100000 20h 01000000 40h 10000000 80h 只需要測試2的次方數(power-of-2)的那些位址

Device test Target 測試memory中的每個bit都可以保存0或是1的值 Offset Value Inverted 00h 00000001 11111110 01h 00000010 11111101 02h 00000011 11111100 03h 00000100 11111011 : FEh 11111111 00000000 FFh

JTAG interface

JTAG interface

JTAG interface

JTAG advantage

How it works? SRAM - on DE2 JTAG - on DE2 I.O.I. (interface of interface) - on DE2 TEST Case - on PC

Block Diagram Why I.O.I.? Tester SRAM Test Case JTAG Error1 Error2 8+64 8 64 1 Error2 I.O.I. TMS, TDI, display 提供多種error版本讓tester偵測 : When error is detected LCM Display

Communication (PC & DE2) RS232!!!

Baud Rate

Baud Rate

SRAM [johnny751125] hcsoso、jackson59、Sinze

Implementation of SRAM 內部電線 data_bus_in_signal data_bus_out_signal address_signal 外部電線 data_bus_in (8-bits) data_bus_out (8-bits) address (4-bits) gw oe

Implementation of SRAM

Error of SRAM 內部線路的誤接 內部線路的短路 write enable和output enable的error 內部input線路永遠連結到0 or 1 內部output線路永遠連結到0 or 1 內部address線路永遠連結到0 or 1 內部線路的短路 內部input線路之間的短路 內部output線路之間的短路 內部address線路之間的短路 write enable和output enable的error

Error of SRAM error1系列：data_bus_in_signal有一個bit的資料會永遠是0 (1_1~1_8) or 1 (1_9~2_16) error2系列：data_bus_out有一個bit的資料會永遠是 0(2_1~2_8) or 1 (2_9~2_16) error3系列：address_signal有一個bit的資料會永遠是 0(3_1~3_2) or 1 (3_3~3_4) error4系列：data_bus_in_signal相鄰的bit短路 error5系列：data_bus_out相鄰的bit短路 error6系列：address_signal相鄰的bit短路 error7系列：output enable(oe)和write enable(gw)的錯誤， 7_1是永遠都在寫，7_2是永遠不會寫，7_3是永遠不會讀

SRAM Video play

JTAG [kcir] mimi9126、troychang、JAST、 gomibako、reeetingay

Implementation Overview

JTAG File Hierarchy

RS232 Buffer File Hierarchy

Problems we met

萬丈project平地起: JTAG Spec JTAG specification: IEEE1149.1 要錢?!

萬丈project平地起: JTAG Spec Specification Sources Boundary-Scan Tutorial 2007 (web resource) The Boundary-Scan Handbook (Parker 1992) What is JTAG: Specification details TDO outputs on falling edge TDI inputs on rising clock edge “The last shift occurs on the transition leaving the state” Spec沒有寫到的部份怎麼辦? 真的要照Spec寫……嗎?

Implementation: Fanout

Implementation: Fanout

Implementation: Fanout Solution: 加and gates outputTCK <= ClockDR and Mode; I1: for i in 0 to 7 generate inputTCKarray(i) <= inputTCK and Mode; outputTCKarray(i) <= outputTCK and Mode; end generate I1; data_bus_out_bsc : bsc port map( sram_data_bus_out( i - 1 ), bsc_link_data_bus_out( i ), outputShiftarray(i mod 8), Mode, outputTCKarray(i mod 8), outputUpdatearray(i mod 8), exit_data_bus_out( i - 1 ), bsc_link_data_bus_out( i - 1 ) )

Implementation: Fanout

Implementation: Fanout Still don’t know how to make an ‘and’ gate appear……. TCK1 <= TCK and TCK X TCK1 <= TCK and 1 X TCK1 <= TCK and TCK and TCK and … X TCK1 <= TCK and Mode O

Implementation:這兩個明明一樣 CRASH!!!! PASS!!! if oe = '0' and gw = '1' then xxx if gw = '0‘ if gw = '1' then if oe = '0' then xxx elsif gw = '0' then 事後推測可能是有Hazard 修改code時莫明奇妙的好了, 所以當時沒有多做測試

傳說中的Hazard?! Functional Timing

傳說中的Hazard?! Simulation Timing simulation vs Functional Simulation

傳說中的Hazard?!

傳說中的Hazard?! if(ShiftIRmap = '1') then TDO <= TDO_from_IR; elsif(ShiftDRmap = '1') then TDO <= TDO_from_DR; else TDO <= 'Z'; end if;

傳說中的Hazard?! 罪魁禍首 ClockDR <= TCK and (ShiftDR_signal or CaptureDR_signal)

傳說中的Hazard?! Solution 1: Asynchronous  Synchronous 不會在value還沒穩定時讀值 Flip flop instead of a latch Solution 2: 把value change的時間從rising edge換成falling edge 於是在rising edge讀值時，所有值都穩定了 (不會和JTAG spec衝突)

傳說中的Hazard?! Other symptoms 莫名的多一次shift JTAG與SRAM合併 JTAG與RS232合併 Conclusion: Hazard是一路伴隨著我們 project從無到有的好朋友 -.-

JTAG Waveform

JTAG Waveform

How to test?

How to test? 用C程式(real_tester.c)產生出waveform檔

How to test? Run Simulation

How to test? 將跑出來的結果上傳至工作站

How to test? 用另一個C程式(wave_checker.c)去比對 結果

Simulation – Data Bus for (i = 0; i < INTEGER_BIT; i++) { write_board(0, 1 << i); read_board(0, 1 << i); }

Simulation – Data Bus

Simulation – Data Bus

Simulation – Data Bus

Simulation – Data Bus

Simulation – Data Bus

Simulation – Address Bus write_board(0, cpattern); for (i = 0; i < ADDRESS_BIT; i++) read_board(1 << i, pattern);

Simulation – Address Bus

Simulation – Address Bus

Simulation – Others

What We Have Learned 分工的困難 Code 合併會花很多時間 之前沒出現的hazard都因為線路delay改了 而出現

Reference http://www.fh-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html http://www.boundary-scan.co.uk/page7.html http://en.wikipedia.org/wiki/Jtag http://en.wikipedia.org/wiki/Boundary_scan http://www.jtag.com/main.php http://www.csie.ntu.edu.tw/~b92036/pub/Boundary- Scan_Tutorial_2007.pdf http://www.csie.ntu.edu.tw/~b94065/.DSD/blockdiagram.jpg http://www.jtag.tk/ http://www.netrino.com/Embedded-Systems/How-To/Memory-Test-Suite-C

Our Website http://www.csie.ntu.edu.tw/~b94097/DSD/website /Home.html