醫工所碩士二年級 R90548009 葉昱甫 電子所碩士一年級 R91943057 謝博鈞 電信所碩士一年級 R91942041 王欣平 Group 6 醫工所碩士二年級 R90548009 葉昱甫 電子所碩士一年級 R91943057 謝博鈞 電信所碩士一年級 R91942041 王欣平
Outline HW/SW Partition Design Hardware Design Simulation Model
Accumulative Multiplication Suitable for Hardware Processing
Also suitable for Hardware
Quantization It is basically a set of division operations and a simple table lookup. Suitable for Hardware
Zigzag scan Huffman Coding Reordering of sequence Not suitable for HW Pure table lookup Suitable for Software
Design Block Diagram Hardware RGB to YUV 8x8 Blocks DCT Quantization Compressed Image Huffman Coding Zigzag Scan Software
Timing diagram
MYIP
Syntax 1.Check error Top Module Sub module 1 Make File Sub module 2 2.Auto make hierarchy for design Top Module Sub module 1 Make File Sub module 2 Net.v Xilinx Sub module 4 Sub module3 design script
Simulation environment Environment TOP Sub module 1 Sub module 2 Sub module3 Sub module 4 design ARM AHBA Test pattern model
Net.v
Conclusion After knowing the algorithms, we try to make a good HW/SW Partition We design the block diagram of Hardware We try to make a Simulation Model, which can guarantee the Hardware can work