Chapter 5 Data Acquisition Circuits Prof. Dehan Luo 第五章 数据采集电路 Section One Sample and hold （第一节 采样与保持） 1、Architecture of data acquisition systems 2、Sample & hold and Basic S/H circuit 3、S/H response characteristics Section Two Multiplexing circuits（第二节 多路开关电路） 1、Multiplexers 2、FET analog switches Section Three Analog to digital converters（第三节 模数转换器） 1、 Single slope or ramp 2、 Successive approximation 3、Dual slope 4、Parallel or ‘flash’ Section Four Digital to analog converters （第四节 数模转换器） 1、Binary weighted ladder 2、R-2R ladder 3、Pulse width modulation Intelligent Sensors System 5-1 School of Information Engineering

Section One Sample and hold Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Section One Sample and hold 第一节 采样与保持 Architecture of data acquisition systems Intelligent Sensors System 5-2 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Sample & hold and Basic S/H circuit 1、A Sample and hold (S/H) circuit has two basic operating modes（采样与 保持电路有两种基本工作方式） （a）Sample mode: The output follows the input （b）Hold mode: The output is held constant until sample mode is resumed （输出保持不变直到采样方式恢复） 2、The main application of S/H circuits is to hold the input signal to an ADC constant during conversion （采样保持电路主要应用是使加到ADC上的 信号在AD转换期间保持不变） Intelligent Sensors System 5-3 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Sample & hold and Basic S/H circuit (Cont.)（续） 3、Basic S/H circuit （基本采样与保持电路） （1） Basic elements （基本元件）： Voltage followers（电压跟随器）， FET switch（场效应开关） （2） Operation（工作原理） IC1 provides low Zout version of input signal Q1 passes the signal during ‘sample’ and disconnects during ‘hold’ C preserves the value during ‘hold’ IC2 is a high Zin op-amp to minimize capacitor discharge during ‘hold’ Intelligent Sensors System 5-4 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Sample & hold and Basic S/H circuit (Cont.)（续） 3、S/H Response parameters（采样/保持电路响应参数） （1）Aperture time: time required for the switch to open (~50ns) （2）Droop: capacitor discharge （3）Acquisition time: switch operation plus capacitor charging time Intelligent Sensors System 5-5 School of Information Engineering 开关闭合电容充电 开关断开时间 电容放电时间

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Sample & hold and Basic S/H circuit (Cont.)（续） 4、Considerations for choosing C（电容C的选择） （1）C should be large enough to minimize ‘droop’ caused by leakage currents in Q1 and IC2（电容C应大的足以使因Q1和 IC2漏电流而引起的放电为最小） （2）C should be small enough to track fast signals since it forms a low-pass filter with Q1’s ON resistance! （电容C应小的足以快速跟 踪低通滤波器输出信号，低通滤波器与Q1的导通电阻有关） （3）In practice, the slew rate of the entire circuit is determined by IC1’s output current and Q1’s ON resistance（实践中，工作周期 由IC1的输出电流和Q1的导通电阻确定） Intelligent Sensors System 5-6 School of Information Engineering

Section Two Multiplexing circuits Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Section Two Multiplexing circuits （第二节 多路开关电路） Multiplexers A multiplexer is a circuit that allows you to select any of several inputs, as specified by digital control signals （多路开关是由数字控制信号确定多路输入 信号中任一路接通的电路） Since analog switches are bi-directional, this circuit could also be used as a de-multiplexer!（由于模拟开关是双向的， 它也可以用于反向多路开关） It could also be uses as a digital MUX since logic levels are just voltages （它也可以用于数字多路开关，因为逻辑电平是电压） Intelligent Sensors System 5-7 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Multiplexing circuits (Cont.) （多路开关电路）（续） FET analog switches （1）N-channel enhancement-mode MOS-FET （采用N型通到MOS-FET 场效应管） （2）When Gate is grounded or negative, the FET is non-conducting and Drain- source resistance in the order of 10,000M （当门极接地或为负电平时，场效应管截止, （3）Bringing the Gate to +15V puts the drain source channel into conduction and Drain-source resistance in the order of 100. （门极加15V电压，使源极场效应管导通,此时，源极电阻为100数量级） Intelligent Sensors System 5-8 School of Information Engineering

Section Three Analog to digital converters Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Section Three Analog to digital converters （第三节 模数转换器） Single slope or ramp 1、 Composed of three basic elements（三个基本元件组成） (1) A binary counter （二进制计数器） (2) A digital-to-analog converter （数模转换器） (3) An analog comparator (模拟电压比较器） Intelligent Sensors System 5-9 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Single slope or ramp（Cont.)（续） 2、Operation（工作过程） Counter is reset Analog input is sampled While VA > VB counter increments When VA=VB counter stops and binary code is available at the output （当VA=VB ，计数器停止计数， 输出端输出二进制数） 3、Characteristics（特点） Relatively slow since conversion time could be up to 2N, where N is the resolution of the ADC （由于转化次数可能达到2N ，速度较慢，N是ADC分辨率） Intelligent Sensors System 5-10 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Successive approximation ADC （连续逼近式ADC） 1、 Basic architecture and elements (基本结构和元件） A digital-to-analog converter An analog comparator A control logic module（控制逻辑模块） A successive approx. register（连续逼近式寄存器） Intelligent Sensors System 5-11 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Successive approximation ADC （连续逼近式ADC）（续） 2、Operation is based on a binary search （基于二进制搜索比较的工作过程） （1） Initially, the register provides an output corresponding to half the range (1000…0) （初始时， 寄存器提供输出 范围的一半值） （2） If the analog input is greater, then MSB=1, else MSB=0 （输入大于寄 存器值，最高位MSB=1否则MSB=0） （3）The register performs the same operation from MSB to LSB （寄存器从最高位到最低位重复执行这一过程） Intelligent Sensors System 5-12 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Successive approximation ADC （连续逼近式ADC）（续） 3、Characteristics（特点） （1） Conversion requires only N steps, where N is the resolution of the ADC（转换只需要N步， N是ADC分辨率） （2） Conversion times of μs are typical（典型的转换时间是微秒级） Intelligent Sensors System 5-13 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Dual slope ADC（双斜坡（双积分）A/D转换器） 1、Architecture （电路结构） Intelligent Sensors System 5-14 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Dual slope ADC（双斜坡（双积分）A/D转换器）（续） 2、Basic elements An integrator （积分器） A zero-crossing detector （过零检测器） A binary counter （二进制计数器） Logic gates and switches （逻辑门和开关） Intelligent Sensors System 5-15 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Dual slope ADC（双斜坡（双积分）A/D转换器）（续） 3、Characteristics （1）Very high resolution, but also slower (30 conversions/sec) （高分辨率，但速度慢，30次/秒） （2） Insensitive to clock drift, RC drifts and high-frequency noise （ 对时钟漂移，RC漂移， 和高频噪声不敏感） （3）Widely used in digital multi-meters广泛用于数字式万用表） Intelligent Sensors System 5-15 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Dual slope ADC（双斜坡（双积分）A/D转换器）（续） 4、 Operation （1）Counter is reset and switch is connected to the analog input（计数器被复位， 开关被连接到模拟输入） （2）The integrator generates a negative ramp whose slope is proportional to the analog input (积分器 产生负斜坡，其斜率正 比于输入） Intelligent Sensors System 5-16 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Dual slope ADC（双斜坡（双积分）A/D转换器）（续） 4、 Operation （3）The comparator goes HIGH, enabling clock pulses into the counter（比较器输出变为高电平， 使输入脉冲进入计数器） （4）When counter overflows, it resets to zero and the control circuit switches the switch to a reference negative voltage （当计数器溢出时，被复位为零， 控制电路切换开关到负参考电压端） （a）This causes the integrator to generate a positive slope ramp （b）When this ramp reaches zero, the comparator goes low and stops the counter, whose value represents the analog input Intelligent Sensors System 5-16 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Parallel or flash ADC （并联或快速A/D转换器） 1、Architecture （电路结构） 2、Basic elements （基本元件） A multiple voltage divider （多倍电压分压器） A set of comparators （一组电压比较器） A priority encoder （优先权编码器） Intelligent Sensors System 5-17 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Parallel or flash ADC （并联或快速A/D转换器）（续） 3 、Operation （1）Analog input applied to all comparators（模拟输入加到比较器） （2）Priority encoder converts comparator pattern into binary （优先编码器转换比较器输出为二进制数） 4、Characteristics （1） Very fast (e.g., 8-bit ADCs capable of 20 million conversions/sec) （转换速度非常快） （2）Very expensive for large N since the number of comparators is 2N-1 （由于使用2N-1个比较器，所以非常贵） Intelligent Sensors System 5-18 School of Information Engineering

Section Four Digital to Analog converters Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Section Four Digital to Analog converters （第四节 数模转换器） Binary weighted ladder (二进制加权梯形电路） 1、Architecture Based on the summing op-amp circuit from chapter 4 （基于第四章中的求和放大器） （1）Each input resistor is twice the value of the previous one （每个电阻值是前一个电阻值的两倍） （2）Inputs are weighted according to their resistors （输入根据其电阻值被加权） Intelligent Sensors System 5-19 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Binary weighted ladder (二进制加权梯形电路）（续） 2、 Characteristics （1）The lowest value resistor R affects the MSB and must have the highest precision （最低位电阻影响最高位， 必须有高精度） （2）This circuit is impractical for large N since it would require high precision resistors for a wide range （本电路对大N不实用，因为在大范围中需要高精度电阻） Intelligent Sensors System 5-20 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo R-2R ladder (R-2R梯形电路） 1、 Basic architecture and elements （1）2 N resistors ( 2N个电阻 ） （2）An op-amp （一个运算放大器） （3）N switches （N个开关） Intelligent Sensors System 5-21 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo R-2R ladder (R-2R梯形电路）（续） 2、Operation （1）Switches When bit Ik=1, the corresponding switch is connected to VREF When bit Ik=0, the corresponding switch is connected to GND （2）Assume all the legs but one are grounded （a）The one connected to VREF will generate a current that flows towards the inverting input of the op-amp (接入VREF引脚产生电流流入运算放大器反相端） （b）This current is halved by the resistor network at each node （该电流在每个节点被二分之一分流） （c）Therefore, the current contribution of each input is weighted by its position in the binary number （因此，每个输入电流由其所在位置的二进制数加权 Intelligent Sensors System 5-22 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo R-2R ladder (R-2R梯形电路）（续） 3、The R-2R operation is better understood by redrawing the resistor network（重画 电路更容易理解R-2R电路的工作） （1）In (b) only the MSB is ON（图b中只有最 高位MSB接通） （2）In (c) only the next bit to the MSB is ON （图c中只有次高位接通） Intelligent Sensors System 5-23 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Pulse Width Modulation 1、 Basic architecture and components （1）A digital line（数字链/数字脉冲） （2）An RC low-pass filter（RC低通滤波器） Intelligent Sensors System 5-24 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo Pulse Width Modulation （Cont.）（续） 2、Operation （1）The digital line is used to generate a train of pulses of fixed frequency（数字链用于产生固定频率的脉冲链） （2）The width (duty cycle) of the pulse is made proportional to the desired analog output（脉冲宽度（占空比）想要的模拟输出） （3）The pulse train is then passed through a low-pass filter, which generates an output voltage proportional to the average time spent in the HIGH state（脉冲链正通过低通滤波器，产生一个正 比于高平状态平均时间的输出电压） Intelligent Sensors System 5-25 School of Information Engineering

Chapter 5 Data Acquisition Circuits Prof. Dehan Luo References 1、D. C. Ramsay, 1996, Principles of Engineering Instrumentation, Arnold, London, UK 2、 H. R. Taylor, 1997, Data Acquisition for Sensor Systems, Chapman and Hall, London, UK. 3、P. Horowitz and W. Hill, 1989, The Art of Electronics, 2nd Ed., Cambridge University Press, Cambridge, UK 4、 J. Brignell and N. White, 1996, Intelligent Sensor Systems, 2nd Ed., IOP, Bristol, UK. 5、R. S. Figliola and D.E. Beasley, Theory and design of Mechanical Measurements, 3rd Ed., Wiley, New York. Intelligent Sensors System 5-26 School of Information Engineering