讲义第十章 微处理器设计.

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1 讲义第十章 微处理器设计

2 以微处理器为中心的数字系统 Sensor Nets Cameras Games Set-top boxes Media Players
Laptops Servers Robots Routers Smart phones Automobiles Supercomputers

3 10.1 微处理器结构 什么是微处理器？ 微处理器的主要结构 微处理器由一片或少数几片大规模集成电路组成的中央处理器。
这些电路执行控制部件和算术逻辑部件的功能。 微处理器能完成取指令、执行指令，以及与外界存储器和逻辑部件交换信息等操作，是微型计算机的运算控制部分。 微处理器的主要结构 冯诺依曼结构 将程序存储和数据存储放在同一物理存储空间 相同的总线 硬件简单 哈佛结构 将程序存储和数据存储分别放在不同的物理存储空间 不同的总线 灵活、速度快

4 冯诺依曼计算机模型 四个主要组成部分 输入、 输出、 存储器 微处理器 冯诺依曼计算机模型

5 微处理器内部结构 微处理器的两个主要部分： 控制单元 用于控制数据通路的所有操作，实现微处理器运算的正确性 数据通路
主要包括运算单元ALU、存储单元（寄存器）及其相互连接 微处理器内部结构

6 指令集 专门执行一些指令集的微处理器 利用指令集编写不同的程序完成不同的处理任务 需要多少条指令集？ 每条指令是什么？
每条指令的操作码（opcode）是什么？ 指令编码使用多少位宽的数据？ 微处理器整体结构 程序指针（Program Counter, PC）寄存器 指令寄存器（Instruction Register, IR） RISC CISC

7 微处理器的三个执行步骤 指令周期 （1）取指 即从程序存储器中把PC所指向的指令取出，拷贝到IR ； PC+1指向下一条指令的地址； （2）译指 从IR中提取出操作码，对指令所要做的操作进行翻译； 决定当前执行那一条指令，跳转到那一个对应的状态去； （3）执行指令 每一步将在有限状态机的一个状态被执行。 每个指令通常在一个时钟周期内执行 有些情况下一些存储器操作的指令可能需要两个甚至更长的时钟周期，这种情况下就需要更多的状态来实现正确的时序。 一般而言，程序的指令都是存储在外部寄存器中的，所以除了CPU外，微处理器一般还需要外部存储器以及连接外部存储器与CPU的地址以及数据总线。

8 微处理器实例分析 --------simple 4-bit CPU

9 CPU design CPU does simple things moving data from/to memory locations
making operations on it Program flow should be allowed to change IO latches are needed for real world operation

10 Registers Registers 是处理器的基本部件.
They serve as most used and useful memory locations, source or target of most of instructions. 74HCT574是8位锁存器latch，它在WE信号的上升沿从数据总线 DB锁存数据. 利用总线驱动器74HCT245，这个数据能在 OE控制下返回到DB总线. We can have a lot of registers on single bus, with WE and OE signals for each one register.

11 ALU 74LS181是4-bit wide ALU 能执行所有常用的logical和arithmetic运算.
Let's put two registers together, add and serve with single bus driver. We have two registers (A and B), ALU, with operation controlled by signals on M and S1 to S4 signals controlled by respective OE and WE signals Because 74LS181 doesn't have tristate outputs for connecting to DB, bus driver is needed here So, data in both registers (accessible from DB) can be passed through ALU and put on DB again.

12 ALU实现的功能 要实现：一个数据放在A,另一个数据到B, 执行 ALU运算，再把结果放到 A.
需要把A数据放到bus, 变高再变低AWE（锁存）,然后把B数据放到bus,变高再变低BWE. 同时, ALU执行运算(它是组合电路)，结果在F1 to F4输出. 我们需要变高ALUOE，结果输出到bus. 如果要写到A寄存器, 需要变高AWE... but wait. 如果我们变高WE, 锁存的数据(ALU result)出现在A register的数据线, ALU的输出也改变了，又传输到A寄存器. 所以我们需要第三个register，叫做T - temporary register. ALU内容输出到bus：先写到T register然后再 (when ALU output is securely saved)到A register.

13 PC program counter – PC It's main job is to increment whenever new instruction is needed or set to value when program jump is to be made. 两个级联74HCT193计数器, EEPROM存储器放着program 和 instruction register (IR). 它存放当前instruction byte直到全部被执行. 计数器的预置输入(A, B, C and D)连到BD, 为了允许直接改变PC (program jump). 否则 PC在每个single instruction之后才改变(+1)， by CLOCK UP signal (pin 5).

14 Instruction decoder, part one
PC and registers with ALU are muscles of CPU, doing hard work, but it needs a brain to decide when and how to change control signals. Instruction decoder does this job. Now starts the real fun and messing with 74xx logic. Before actually building instruction decoder, it is necessary to decide which instructions we are going to decode.

15 Instructions For this computer, I decided to use only three instructions: 1, load direct data to A 2, move data from source to destination. Source can be A, B, RAM or input registers; destination can be A, B, PC, RAM or output registers. 3, do ALU operation between A and B, move result to A Allowing PC to be result of move allows jumps. You can transfer input data from IO port to RAM in single instruction. RAM is treated as another register, with address bus connected to B register. So, B is address pointer for RAM operation. Some move instructions have to affect on registers or memory. Example is move A to A. This could be equivalent of NOP instruction. There is no dedicated indirect addressing register, no stack, no interrupts.

16 Instructions MSB of instruction determines whether instruction is LDI.
We need to waste only one bit for this, so 7 bits are used as immediate data. As immediate data are one of sources for jump instructions, this allows addressing 128B of program ROM. In fact, data from ALU (computed jump) can be used for jumping but this address is only 4 bits wide, allowing addressing 16B of ROM, leaving this option as not very useful. If MSB is zero, next bit determines MOV or ALU instruction notice how this step by step description determines real operation of instruction decoder.

17 Instruction timing Instructions are divided into single steps. In our case, we will have for steps, let's call it machine cycles. M1: load instruction to IR and put source data on DB M2: load source data from bus to T register M3: put data from T register on DB M4: load data from DB to destination, increment PC CLK M1 M2 M3 M4 黑色方块表示active (高) 电平. CLK是输入时钟信号. 全指令做完需要eight cycles.

18 Instruction set Instruction set is simple: 7 6 5 4 3 2 1 MOVI
MOVI IMMEDIATE DATA MOV SRC DST ALU X M S3 S2 S1 S0 If 实际指令是MOVI, 源数据是 lower 7 bits from IR, 目标destination is A If实际指令是MOV,源数据是 determined by IR[3..5] and目标destination by IR[0..2] If实际指令是ALU,源数据是from ALU bus driver,目标destination is A This gives us first clue about instruction register operation. Notice 前沿of M2 comes while M1 is still high. This 重叠 is needed to 安全写数据到 T register. 同样for M3 and M4.

19 CLOCK 时钟电路很简单. We need D-flip-flop, 除以2, 使clock有4个可能的状态.
Those states 解码by simple AND logic. To achieve 1:1 duty cycle of incoming clock signal from 555 timer, second D-FF is used.

20 Instruction decoder, part two
Knowing what a how to decode, we can proceed in design of instruction decoder. Let‘s最复杂的instruction开始, MOV. 我们需要选择源register during phase M1 and put on bus so OE signal of selected register要有效during M1 phase. 我们可以使用74HCT138 1-of-8译码器. Fortunately它有3个芯片选择脚, two of them inverted. We can connect those two to IR[7] and IR[6] signals, thus activating during MOV instruction. Third, high active, select pin is connected to M1 signal. The same goes for selecting destination register, with the exception that third chip select pin goes to M4 signal. 为了完成MOV instruction, 我们需要小心对待T register. OE of T register will be active during M3 and WE during M2. MOVI and ALU instructions are very alike, except of that first one select IROE signal, while former selects ALUOE signal during M1. AWE (write to A register) is active during M4 for both instructions.

21 Instruction decoder IC20, IC21 and IC22 does this job
generates IROE and ALUOE signals, as well as AWE signal. For this purpose I used simple looking, but useful software, Logic Friday. I generated this truth table for AWE signal

22 Decoder circuit of logic gates
and software minimized this table into equations and generated circuit of logic gates doing the same job.

23 Decoder circuit I did the same for IROE and ALUOE signals.
Voila, instruction decoder is done. We need to make jumps conditional in some way. I decided to use register B for this purpose. When it's content is 0xF, jump (MOV to PC) is executed as NOP. Notice, on final schematics, signal M3 is not used at all. It is needed for latching output of T register, but M1 is used, as driver expects negative logic and M3 is only inverted M1.

24

25 Input/output ports The only thing not described for now is IO part.
We have two signals from 138 decoders, so all is needed is double 4-bit bus driver (IC25) for input ports and two 4-bit wide latches as output ports (IC26, IC27).

26 ALL SCHEMATIC

27 Programming As our CPU is basically done, we need to program it to make something useful. Lets start with simple program - emulation of four NAND gates. MOV IA,A ; move data from input A to register A MOV IB,B ; move data from input B to register B ALU NAND ; do NAND operation MOV A,PA ; move data from A (ALU result) to port A MOVI ; move zero to A MOV A,B ; move this zero to B MOV A, PC ; jump to zero

28 Assembly Quick hand assembly gives this output 0x20 0x29 0x54 0x04

29 Burning That is ready to be burned into EEPROM.
I used Genius G540 programmer really low cost, but it does its job.

30 Result, or 7400^2 to 7400^x Circuit was built on perfboard with dimension cca 18x18cm. Current consumption is about 180mA, majority of this is drawn by and in plain old TTL technology. Clock speed is determined by C1 capacitor. For 1uF, clock generator ticks at about 80Hz, giving 10Hz execution speed. For no capacitor, oscillator works at frequency given by stray capacitance, resulting in cca 57kHz execution speed. Yes, whopping 57,000 instructions per second.

31 微处理器完整电路 数据通路、控制单元电路（控制和状态信号）

32 总结 ALU 时钟 PC计数器 寄存器 程序存储器 寄存器组 总线

33 4bit Simple CPU ALU 时钟 PC计数器 寄存器 程序存储器 寄存器组 总线
Spring ZDMC – Lec. #1 – 1

34 4bit Simple CPU Spring ZDMC – Lec. #1 – 1

35 参考资料 Spring ZDMC – Lec. #1 – 1

36 数字系统设计 Digital System Design
EE141 数字系统设计 Digital System Design ------微处理器设计 王维东 Weidong Wang 浙江大学信息与电子工程学院 College of Information Science & Electronic Engineering Zhejiang University 2015 ZDMC – Lec. #1 – 44