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90nm 標準MOS 元件製作流程 (Metal-Oxide-Semiconductor devices fabrication flow)
矽基板清潔 (Wafer clean) 薄膜沉積與曝光 (Film deposition and Lithography) 薄膜蝕刻 (Film etch) 離子佈植與氧化 (Ion implantation and Oxidation) * 薄膜移除,沉積與曝光 (Film strip;film deposition and Lithography) 金屬薄膜沉績 (Option) (Metal film deposition ) *離子佈植與熱退火 (Ion implantation and Thermal annealing) *薄膜沉積與蝕刻 (Film deposition and Etch) *離子佈植 (Ion implantation) *薄膜蝕刻 (Film etch) 熱退火與薄膜去除 (Thermal annealing and Metal film strip ) 薄膜沉積與化學機械研磨 (Film deposition and CMP) 曝光 (Lithography) 薄膜沉績與金屬薄膜沉積(Film etch and Metal film deposition ) 金屬薄膜蝕刻 (Metal film etch) 紅字為 90nm元件之關鍵製程, 下run前請與工程師討論.
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90nm 標準MOS 元件 v0.1 Base-Line條件
NMOS PMOS Vt implant BF2,90K 1E13 As, 80K 8E12 APT implant B,100K 7E12 P,120K 4E12 Gate oxide Gox20A Poly gate Poly(Undoped)1200A Reoxidation reox 50A PKT NPKT1:BF2,50keV,5E12,Tilt45D,Twist27D, Rotation:4 PPKT2:As,50keV,2E12,Tilt45D,Twist27D, SD-extension As,7keV,1E15 BF2,7keV,5E14 MSW spacer SiN MSW 1200A (780C) SD implant NMOS SD AS 20K 5E15 PMOS SD BF2 15K 5E15 RTA SD RTA 1050C, 10SEC
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