数字系统设计 Digital System Design EE141 数字系统设计 Digital System Design ------触发器与存储电路 王维东 Weidong Wang 浙江大学信息与电子工程学院 College of Information Science & Electronic Engineering 信息与通信网络研究所 Zhejiang University Spring 2018 – Lec. #6

任课教师 王维东 TA: 浙江大学信息与电子工程学院, 信电楼306 邮箱：wdwang@zju.edu.cn EE141 任课教师 王维东 浙江大学信息与电子工程学院, 信电楼306 邮箱：wdwang@zju.edu.cn College of Information Science & Electronic Engineering Zhejiang University, Hangzhou, 310027 Tel: 86-571-87953170 (O) Mobile: 13605812196 TA: 陈 佳云 Jiayun CHEN，13161700140; chenjy93@outlook.com; 陈 彬彬 Binbin CHEN, 13071888906; 15091831397@163.com； Office Hours：玉泉信电楼 308室（可以微信或邮件联系）. Spring 2018 – Lec. #6

Prerequisites预修课程 电子电路基础 电子线路 C语言 How to learn this Course? Not only listening, thinking and waiting …. But Exercise, Simulation, Practice!

课程简介 课程代码：111C0120 参考书 阎石, 数字电子技术基础, 第6版, 高等教育出版社, 2016. EE141 课程简介 课程代码：111C0120 参考书 阎石, 数字电子技术基础, 第6版, 高等教育出版社, 2016. 王金明著，数字系统设计与Verilog HDL，电子工业出版社，第6版 补充讲义/期中考试前预备 Stanford 大学 108A课程notes. R.H.Katz, G.Borriello, Contemporary Logic Design, second edition,电子工业出版社, 2005. M.M.Mano, 数字设计(第四版), 电子工业出版社, 2010. http://www.prenhall.com/mano Spring 2018 – Lec. #6

Other Course Info Website: http://mypage.zju.edu.cn/wdwd/教学工作/ Check frequently 答疑 玉泉信电楼308室/周三周五下午2:30-5:00 上课课间、课后均可 Email，微信群/数字系统设计2018，短信均可

Grading (考核) Final grades will be computed approximately as follows: 平时（含课程作业、期中考试+小测验、Project、出勤等）30% Class Room Check Homework Sets 作业每周三上交截止期为课后一周内有效。 Project 2 projects (1 or 2 members team) Project-2可选（总评加分1~5分，但不超过平时成绩范围） Finial Exam期末闭卷考试 - 70% 上课说明此门课程的成绩合成：平时成绩包括平时小测验、期中考试、作业、出勤、课堂讨论、论文

授课时间和地点： 2017年春夏学期， 地点：紫金港西2-309(多) 周三上午，第1~2节(8:00-9:35) 星期五上午，第1~2节(8:00-9:35) 地点：紫金港西2-309(多) http://mypage.zju.edu.cn/wdwd/教学工作/ 学在浙里/数字系统设计2018

课程简介 课程代码：111C0120 参考书 阎石, 数字电子技术基础, 第6版, 高等教育出版社, 2016. EE141 课程简介 课程代码：111C0120 参考书 阎石, 数字电子技术基础, 第6版, 高等教育出版社, 2016. 王金明著，数字系统设计与Verilog HDL，电子工业出版社，第6版 补充讲义/期中考试前预备 Stanford 大学 108A课程notes. R.H.Katz, G.Borriello, Contemporary Logic Design, second edition,电子工业出版社, 2005. M.M.Mano, 数字设计(第四版), 电子工业出版社, 2010. http://www.prenhall.com/mano Spring 2018 – Lec. #6

课程结构 数字理论知识(必备) 数字电路分析与设计 脉冲电路与接口 控制器与数字系统 微处理器简介与设计 数字系统和编码、逻辑代数、门电路 EE141 课程结构 数字理论知识(必备) 数字系统和编码、逻辑代数、门电路 数字电路分析与设计 组合逻辑电路 触发器、半导体存贮器、可编程器件 时序逻辑电路 脉冲电路与接口 控制器与数字系统 状态机 控制器 微码控制器 测试和验证 微处理器简介与设计 指令集 简单CPU设计 Spring 2018 – Lec. #6

EE141 第五章 时序电路基础之 --- 触发器

Sequential Logic时序逻辑 Sequential Circuits时序 Timing Methodologies定时 EE141 Sequential Logic时序逻辑 Sequential Circuits时序 Simple circuits with feedback Latches记忆元件 Edge-triggered flip-flops啪嗒作响 Timing Methodologies定时 Cascading级联 flip-flops for proper operation Clock skew时钟偏移 Any prior input-level conditions have no effect on the present outputs because combinational logic circuits have no memory. Most digital systems consist of both combinational circuits and memory elements. Spring 2018 – Lec. #6

Sequential Circuits Circuits with Feedback Outputs = f(inputs, past inputs, past outputs) Basis for building "memory" into logic circuits Door combination lock is an example of a sequential circuit State is memory State is an "output" and an "input" to combinational logic Combination storage elements are also memory C1 C2 C3 comparator value equal multiplexer reset open/closed new mux control clock comb. logic state Spring 2018 – Lec. #6

Circuits with Feedback How to control feedback? What stops values from cycling around endlessly X1 X2 • • • Xn switching network Z1 Z2 • • • Zn Spring 2018 – Lec. #6

EE141 触发器 flip-flop 5.1 概述 一、用于记忆1位二进制信号 1. 有两个能自行保持的状态 2. 根据输入信号可以置成0或1 二、分类 1. 按触发方式（电平，脉冲，边沿） 2. 按逻辑功能（RS, JK, D, T） 三、存储器件 ROM、SRAM、DRAM、FLASHROM The most important memory element is the flip-flop, which is made up of an assembly of logic gates. Spring 2018 – Lec. #6

Simplest Circuits with Feedback Two inverters form a static memory cell Will hold value as long as it has power applied How to get a new value into the memory cell? Selectively break feedback path Load new value into cell "0" "1" "stored value" "remember" "load" "data" "stored value" Spring 2018 – Lec. #6

Memory with Cross-coupled Gates EE141 Memory with Cross-coupled Gates Cross-coupled NOR gates Similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1) Cross-coupled NAND gates Similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) R S Q Q' R S Q Q Q' S' R' R' S' Q Spring 2018 – Lec. #6

EE141 5.2 SR锁存器Latch 一、电路结构与工作原理 Spring 2018 – Lec. #6

EE141 1 0① ① Spring 2018 – Lec. #6

Timing Behavior Setup and Hold Times R S Q Q' Reset Hold Set Race R S EE141 Timing Behavior Setup and Hold Times R S Q Q' Reset Hold Set Race R S Q \Q 100 Spring 2018 – Lec. #6

State Behavior of R-S latch EE141 State Behavior of R-S latch Truth table of R-S latch behavior Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 S R Q 0 0 hold 0 1 0 1 0 1 1 1 unstable Spring 2018 – Lec. #6

Theoretical R-S Latch Behavior EE141 Theoretical R-S Latch Behavior SR=10 SR=00 SR=01 SR=00 SR=10 Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 Q Q' 1 1 SR=01 SR=10 SR=01 SR=01 SR=10 SR=11 SR=11 SR=11 State Diagram States: possible values Transitions: changes based on inputs possible oscillation between states 00 and 11 SR=00 SR=00 SR=11 Spring 2018 – Lec. #6

Observed R-S Latch Behavior EE141 Observed R-S Latch Behavior Very difficult to observe R-S latch in the 1-1 state One of R or S usually changes first Ambiguously returns to state 0-1 or 1-0 A so-called "race condition" Or non-deterministic transition SR=00 Q Q' 0 1 Q Q' 1 0 Q Q' 0 0 SR=10 SR=01 SR=11 Spring 2018 – Lec. #6

characteristic equation EE141 R-S Latch Analysis Break feedback path R S Q Q' Q(t) Q(t+) S R S R Q(t) Q(t+) 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 X 1 1 1 X hold reset set not allowed 0 0 1 0 X 1 Q(t) R S characteristic equation Q(t+) = S + R’ Q(t) Spring 2018 – Lec. #6

EE141 二、动作特点 在任何时刻，输入都能直接改变输出的状态。 例： Spring 2018 – Lec. #6

EE141 5.3触发器 5.3.1电平触发的触发器 一、电路结构与工作原理 X 1 1* Spring 2018 – Lec. #6

Gated R-S Latch Control when R and S inputs matter EE141 Gated R-S Latch enable' S' Q' Q R' R S Control when R and S inputs matter Otherwise, the slightest glitch on R or S while enable is low could cause change in value stored Set Reset S' R' enable' Q Q' 100 Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

Clocks Used to keep time Clocks are regular periodic signals Wait long enough for inputs (R' and S') to settle Then allow to have effect on value stored Clocks are regular periodic signals Period (time between ticks) Duty-cycle (time clock is high between ticks - expressed as % of period) duty cycle (in this case, 50%) period Spring 2018 – Lec. #6

Clocks (cont’d) Controlling an R-S latch with a clock EE141 Clocks (cont’d) Controlling an R-S latch with a clock Can't let R and S change while clock is active (allowing R and S to pass) Only have half of clock period for signal changes to propagate Signals must be stable for the other half of clock period clock' S' Q' Q R' R S clock R' and S' changing stable Spring 2018 – Lec. #6

EE141 二、动作特点 在CLK=1的全部时间里， S和R的变化都将引起输出状态的变化。 Spring 2018 – Lec. #6

EE141 D触发器 X 1 1* Spring 2018 – Lec. #6

Cascading Latches Connect output of one latch to input of another EE141 Cascading Latches Connect output of one latch to input of another How to stop changes from racing through chain? Need to control flow of data from one latch to the next Advance from one latch per clock period Worry about logic between latches (arrows) that is too fast clock R S Q Q' Spring 2018 – Lec. #6

提高可靠性，要求每个CLK周期输出状态只能改变1次 EE141 5.3.3 脉冲触发的触发器 提高可靠性，要求每个CLK周期输出状态只能改变1次 一、电路结构与工作原理 Spring 2018 – Lec. #6

Master-Slave Structure EE141 Master-Slave Structure Break flow by alternating clocks (like an air-lock) Use positive clock to latch inputs into one R-S latch Use negative clock to change outputs with another R-S latch View pair as one basic unit master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of clock but does not affect any cascaded flip-flops master stage slave stage P P' CLK R S Q Q' Spring 2018 – Lec. #6

The 1s Catching Problem In first R-S stage of master-slave FF EE141 The 1s Catching Problem In first R-S stage of master-slave FF 0-1-0 glitch on R or S while clock is high “caught” by master stage捕捉 Leads to constraints on logic to be hazard-free master stage slave stage P P' CLK R S Q Q' Set 1s catch S R CLK P P' Q Q' Reset Master Outputs Slave Outputs Spring 2018 – Lec. #6

问：在CLK=1时，如果S=R=1，主输出“11”，在CLK下降沿到来后，主输出会停在“？？” EE141 X 1 1* 问：在CLK=1时，如果S=R=1，主输出“11”，在CLK下降沿到来后，主输出会停在“？？” Spring 2018 – Lec. #6

EE141 把上次的输出加入反馈， 决定输入 J K Q’ 主 从 S R Q CLK Spring 2018 – Lec. #6

EE141 J 主 从 S R K Q Q’ CLK 加入反馈后的效果 Spring 2018 – Lec. #6

(5) 列出真值表 X 1 X 1 1* 主 从 S R J K Q Q’ CLK CLK=1时的脉冲期间， 输入的中间变化会影响输出； EE141 (5) 列出真值表 X 1 X 1 1* 主 从 S R J K Q Q’ CLK CLK=1时的脉冲期间， 输入的中间变化会影响输出； 要分析整个CLK=1的输入， 才能知道输出会是什么。 Spring 2018 – Lec. #6

EE141 二、脉冲触发方式的动作特点 主 从 S R J K Q Q’ CLK Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

D Flip-Flop Make S and R complements of each other EE141 D Flip-Flop Make S and R complements of each other Eliminates 1s catching problem Can't just hold previous value (must have new value ready every clock period) Value of D just before clock goes low is what is stored in flip-flop Can make R-S flip-flop by adding logic to make D = S + R' Q D Q Q' master stage slave stage P P' CLK R S 10 gates Spring 2018 – Lec. #6

EE141 5.3.2边沿触发的触发器 为了提高可靠性，增强抗干扰能力， 希望触发器的次态仅取决于CLK的下降沿（或上升沿）到来 时的输入信号状态，与在此前、后输入的状态没有关系。 实现方式分类: 1)用CMOS传输门的边沿触发器 2)维持阻塞触发器 3)用门电路tpd的边沿触发器 · · · 这样我们不需要分析整个CLK=1期间的输入变化， 只需要分析CLK边沿几个时刻的输入情况。 Spring 2018 – Lec. #6

EE141 一、电路结构和工作原理 1、用两个电平触发D触发器组成的边沿触发器 Spring 2018 – Lec. #6

EE141 边沿触发器 2、用门电路tpd的边沿触发器 45 Spring 2013 ZDMC – Lec. #1 – 5 45

EE141 3.利用CMOS传输门的边沿触发器 X 1 Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

4. Edge-Triggered Flip-Flops维持阻塞型 EE141 4. Edge-Triggered Flip-Flops维持阻塞型 More efficient solution: only 6 gates sensitive to inputs only near edge of clock signal (not while high) Q D Clk=1 R S D’ Q’ negative edge-triggered D flip-flop (D-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input holds D' when clock goes low holds D when clock goes low characteristic equation Q(t+1) = D 48 Spring 2017 ZDMC – Lec. #1 – 6 48

Edge-Triggered Flip-Flops (cont’d) EE141 Edge-Triggered Flip-Flops (cont’d) Step-by-step analysis Q new D Clk=0 R S D D’ Q D Clk=0 R S D’ new D  old D when clock is low data is held when clock goes high-to-low data is latched Spring 2018 – Lec. #6

Edge-Triggered Flip-Flops (cont’d) EE141 Edge-Triggered Flip-Flops (cont’d) D = 0, Clk High 1 Act as inverters D’ D D’ Hold state R Q Clk=1 1 S D D’ D Spring 2018 – Lec. #6

Edge-Triggered Flip-Flops (cont’d) EE141 Edge-Triggered Flip-Flops (cont’d) D = 1, Clk High 1 1 ® 0 0 ® 1 D’ D D’ R Q Clk=1 1 S D 0 ® 1 D’ D 1 Spring 2018 – Lec. #6

Edge-Triggered Flip-Flops (cont’d) EE141 Edge-Triggered Flip-Flops (cont’d) D = 1, Clk LOW 1 Act as inverters D’ D D’ 0 ® 1 R Q Clk=0 1 ® 0 1 S 0 ® 1 D 1 D’ D Spring 2018 – Lec. #6

Edge-Triggered Flip-Flops (cont’d) EE141 Edge-Triggered Flip-Flops (cont’d) Positive edge-triggered Inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops Inputs sampled on falling edge; outputs change after falling edge 100 D CLK Qpos Qpos' Qneg Qneg' positive edge-triggered FF negative edge-triggered FF Spring 2018 – Lec. #6

5. Negative Edge Trigger FF in Verilog module d_ff (q, q_bar, data, clk); input data, clk; output q, q_bar; reg q; assign q_bar = ~q; always @(negedge clk) begin q <= data; end endmodule Spring 2018 – Lec. #6

EE141 5.3.4 触发器的逻辑功能分类 5.6.1 触发器按逻辑功能的分类 时钟控制的触发器中 由于输入方式不同（单端，双端输入）、次态（ ）随输入变化的规则不同 注：如果没有特别指明，以后说的有时钟的触发器默认都是指边沿触发的触发器 Spring 2018 – Lec. #6

一、SR触发器 1. 定义，凡在时钟信号作用下，具有如下功能的触发器称为SR触发器 EE141 一、SR触发器 1. 定义，凡在时钟信号作用下，具有如下功能的触发器称为SR触发器 约束条件 1 1* Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

EE141 二、JK触发器 1.定义 1 Spring 2018 – Lec. #6

Spring 2018 – Lec. #6

EE141 三、T触发器 1. 定义：凡在时钟信号作用下，具有如下功能的触发器 1 Spring 2018 – Lec. #6

EE141 四、D触发器 1. 定义：凡在时钟信号作用下，具有如下功能的触发器 1 。。。。 Spring 2018 – Lec. #6

EE141 逻辑功能： 是 与输入及 在CLK作用后稳态之间的关系 （RS, JK, D, T） 电路结构形式： 具有不同的动作特点（转换状态的动态过程） （同步，主从，边沿） Spring 2018 – Lec. #6

Comparison of Latches and Flip-Flops EE141 Comparison of Latches and Flip-Flops D Q D CLK Qedge Qlatch CLK positive edge-triggered flip-flop D Q G CLK transparent (level-sensitive) latch behavior is the same unless input changes while the clock is high Spring 2018 – Lec. #6

Comparison of Latches and Flip-Flops (cont’d) EE141 Comparison of Latches and Flip-Flops (cont’d) Type When inputs are sampled When output is valid unclocked always propagation delay from input change latch level-sensitive clock high propagation delay from input change latch (Tsu/Th around falling or clock edge (whichever is later) edge of clock) master-slave clock high propagation delay from falling edge flip-flop (Tsu/Th around falling of clock edge of clock) negative clock hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of clock flip-flop edge of clock) Spring 2018 – Lec. #6

EE141 5.3.5 触发器的动态特性 一、输入信号宽度 二、传输延迟时间 Spring 2018 – Lec. #6

一、建立时间 二、保持时间 三、传输延迟时间 四、最高时钟频率 EE141 一、建立时间 二、保持时间 三、传输延迟时间 四、最高时钟频率 Spring 2018 – Lec. #6

Typical Timing Specifications EE141 Typical Timing Specifications Positive edge-triggered D flip-flop Setup and hold times Minimum clock width Propagation delays (low to high, high to low, max and typical) Th 5ns Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns Tsu 20ns D CLK Q all measurements are made from the clocking event that is, the rising edge of the clock Spring 2018 – Lec. #6

POTENTIAL TIMING PROBLEM IN FF CIRCUITS The potential timing problem is this: because Q1 will change on the NGT of the clock pulse, the J2 input of Q2 will be changing as it receives the same NGT. This could lead to an unpredictable response at Q2. Spring 2018 – Lec. #6

Cascading Edge-triggered Flip-Flops级联问题 EE141 Cascading Edge-triggered Flip-Flops级联问题 Shift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) CLK IN Q0 Q1 D Q OUT Fortunately, all modern edge-triggered FFs have hold time requirements that are 5 ns or less; most have tH = 0, which means that they have no hold time requirement. 100 IN Q0 Q1 CLK Spring 2018 – Lec. #6

Cascading Edge-triggered Flip-Flops (cont’d) EE141 Cascading Edge-triggered Flip-Flops (cont’d) Why this works Propagation delays exceed hold times Clock width constraint exceeds setup time This guarantees following stage will latch current value before it changes to new value Tsu 4ns Tp 3ns Th 2ns In Q0 Q1 CLK timing constraints guarantee proper operation of cascaded components assumes infinitely fast distribution of the clock Spring 2018 – Lec. #6

Clock Skew时钟偏移 The problem EE141 Clock Skew时钟偏移 The problem Correct behavior assumes next state of all storage elements determined by all storage elements at the same time Difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay) Effect of skew on cascaded flip-flops: original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1 CLK1 is a delayed version of CLK0 In Q0 Q1 CLK0 CLK1 100 Spring 2018 – Lec. #6

Summary of Latches and Flip-Flops EE141 Summary of Latches and Flip-Flops Development of D-FF Level-sensitive used in custom integrated circuits can be made with 4 switches Edge-triggered used in programmable logic devices Good choice for data storage register Historically J-K FF was popular but now never used Similar to R-S but with 1-1 being used to toggle output (complement state) Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q Not a good choice for PLAs as it requires two inputs Can always be implemented using D-FF Preset and clear inputs are highly desirable on flip-flops Used at start-up or to reset system to a known state Spring 2018 – Lec. #6

Flip-Flop Features Reset (set state to 0): R EE141 Flip-Flop Features Reset (set state to 0): R Synchronous: Dnew = R' • Dold (when next clock edge arrives) Asynchronous: doesn't wait for clock, quick but dangerous Preset or set (set state to 10: S (or sometimes P) Synchronous: Dnew = Dold + S (when next clock edge arrives) Both reset and preset Dnew = R' • Dold + S (set-dominant) Dnew = R' • Dold + R'S (reset-dominant) Selective input capability (input enable/load): LD or EN Multiplexer at input: Dnew = LD' • Q + LD • Dold Load may/may not override reset/set (usually R/S have priority) Complementary outputs: Q and Q' Spring 2018 – Lec. #6

触发器Flip-Flop分类 逻辑功能分类 逻辑功能指按触发器的次态和现态及输入信号之间的逻辑关系. RS锁存器 JK触发器 T触发器 EE141 触发器Flip-Flop分类 逻辑功能分类 RS锁存器 JK触发器 T触发器 D触发器 逻辑功能指按触发器的次态和现态及输入信号之间的逻辑关系. 特性表 特性方程 状态转换图 Spring 2018 – Lec. #6

RS 锁存器 特性方程Qn+1=S+R’Qn RS Latch的状态转换图 特性表/真值表 1 0 1 1 0 0 0 0 0 EE141 RS 锁存器 特性方程Qn+1=S+R’Qn RS Latch的状态转换图 特性表/真值表 1 S=1,R=0 S=0,R=1 S=X,R=0 S=0,R=X S R Qn Qn+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 0 保持 复位 置位 不定 Spring 2018 – Lec. #6

JK 触发器 特性方程:Qn+1=JQn’+K’Qn JK FF的状态转换图 特性表/真值表 1 0 1 1 0 0 0 0 0 EE141 JK 触发器 特性方程:Qn+1=JQn’+K’Qn JK FF的状态转换图 特性表/真值表 1 J=1,K=X J=X,K=1 J=X,K=0 J=0,K=X J K Qn Qn+1 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 保持 复位 置位 翻转 Spring 2018 – Lec. #6

T 触发器 特性方程:Qn+1=TQn’+T’Qn T FF的状态转换图 特性表/真值表 T’触发器：T=1, Qn+1=Qn’ 1 EE141 T 触发器 特性方程:Qn+1=TQn’+T’Qn T FF的状态转换图 特性表/真值表 T’触发器：T=1, Qn+1=Qn’ 1 T=1 T=0 T Qn Qn+1 0 0 0 0 1 1 1 0 1 1 1 0 保持 翻转 JK触发器的两个输入端连在一起作为T端，可以构成T Flip-flop Spring 2018 – Lec. #6

D 触发器 特性方程:Qn+1=D D FF的状态转换图 特性表/真值表 1 1 1 1 0 0 0 0 1 0 1 0 1 D=1 D=0 EE141 D 触发器 特性方程:Qn+1=D D FF的状态转换图 特性表/真值表 1 D=1 D=0 D Qn Qn+1 0 0 0 0 1 0 1 0 1 1 1 1 reset set Spring 2018 – Lec. #6

EE141 采用D 触发器实现JK触发器 K D clk Q Q’ J Clk Spring 2018 – Lec. #6

Timing Methodologies Rules for interconnecting components and clocks EE141 Timing Methodologies Rules for interconnecting components and clocks Guarantee proper operation of system when strictly followed Approach depends on building blocks used for memory elements Focus on systems with edge-triggered flip-flops Found in programmable logic devices Many custom integrated circuits focus on level-sensitive latches Basic rules for correct timing: (1) Correct inputs, with respect to time, are provided to the flip-flops (2) No flip-flop changes state more than once per clocking event Spring 2018 – Lec. #6

Timing Methodologies (cont’d) EE141 Timing Methodologies (cont’d) Definition of terms clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level setup time: minimum time before the clocking event by which the input must be stable (Tsu) hold time: minimum time after the clocking event until which the input must remain stable (Th) input clock Tsu Th clock data changing stable D Q there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized Spring 2018 – Lec. #6

D LATCH (TRANSPARENT LATCH) 5.4 寄存器 D LATCH (TRANSPARENT LATCH) Spring 2018 – Lec. #6

Actual Ics 多位成组 Spring 2018 – Lec. #6

SERIAL DATA TRANSFER: SHIFT REGISTERS Spring 2018 – Lec. #6

EE141 5.5 半导体存储器 A major advantage of digital over analog systems is the ability to store easily large quantities of digital information and data for short or long periods. Spring 2018 – Lec. #6

5.5 半导体存储器 memory devices 1 概述 能存储大量二值信息的器件 一、一般结构形式 ！单元数庞大 EE141 5.5 半导体存储器 memory devices 1 概述 能存储大量二值信息的器件 一、一般结构形式 flip-flop? ！单元数庞大 ！输入/输出引脚数目有限 输入/出电路 I/O 输入/出 控制 Spring 2018 – Lec. #6

（Random-Access-Memory） 2、从工艺分： ①双极型 ②MOS型 EE141 二、分类 1、从存/取功能分： ①只读存储器 (Read-Only-Memory） ②随机读/写 （Random-Access-Memory） 2、从工艺分： ①双极型 ②MOS型 Spring 2018 – Lec. #6

5.5 随机存储器RAM random-access memory EE141 5.5 随机存储器RAM random-access memory 5.5.1 静态随机存储器（SRAM）STATIC RAM 一、结构与工作原理 Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

EE141 二、SRAM的存储单元 六管N沟道增强型MOS管 Spring 2018 – Lec. #6

Logic symbols (a) the 2147H RAM chip; (b) the MCM6206C RAM. Spring 2018 – Lec. #6

Symbol and mode table for the CMOS MCM6264C. Spring 2018 – Lec. #6

5.5.2* 动态随机存储器（DRAM）DYNAMIC RAM EE141 5.5.2* 动态随机存储器（DRAM）DYNAMIC RAM 动态存储单元是利用MOS管栅极电容可以存储电荷的原理 Dynamic RAMs store 1s and 0s as charges on a small MOS capacitor (typically a few picofarads). In modern DRAM chips, each memory cell must be refreshed typically every 2, 4, or 8 ms, or its data will be lost. Spring 2018 – Lec. #6

Cell arrangement in a dynamic RAM DRAM TECHNOLOGY Memory Modules single-in-line memory module (SIMM) dual-in-line memory module (DIMM) SODIMM RIMM DRDRAM FPM DRAM EDO DRAM SDRAM DDRSDRAM SLDRAM Spring 2018 – Lec. #6

Simplified architecture of the TMS44100 ; RAS>CAS timing Spring 2018 – Lec. #6

5.5.3 ROM-READ-ONLY MEMORIES 1 掩模ROM 一、结构 EE141 5.5.3 ROM-READ-ONLY MEMORIES 1 掩模ROM 一、结构 Spring 2018 – Lec. #6

EE141 二、举例 Spring 2018 – Lec. #6

A0~An-1 W(2n-1) Dm Spring 2018 – Lec. #6 W0 D0 地 址 数 据 1 A1 A0 D3 D2 EE141 A0~An-1 W0 W(2n-1) D0 Dm 地 址 数 据 A1 A0 D3 D2 D1 D0 1 Spring 2018 – Lec. #6

两个概念： 存储矩阵的每个交叉点是一个“存储单元”，存储单元中有器件存入“1”，无器件存入“0” 存储器的容量：“字数 x 位数” EE141 两个概念： 存储矩阵的每个交叉点是一个“存储单元”，存储单元中有器件存入“1”，无器件存入“0” 存储器的容量：“字数 x 位数” Spring 2018 – Lec. #6

掩模ROM的特点： 出厂时已经固定，不能更改，适合大量生产 简单，便宜，非易失性nonvolatile EE141 掩模ROM的特点： 出厂时已经固定，不能更改，适合大量生产 简单，便宜，非易失性nonvolatile Spring 2018 – Lec. #6

ROM ARCHITECTURE Spring 2018 – Lec. #6

Typical timing for a ROM read operation. Spring 2018 – Lec. #6

2 可编程ROM（PROM）Programmable ROMs EE141 2 可编程ROM（PROM）Programmable ROMs 总体结构与掩模ROM一样，但存储单元不同 “one-time programmable” (OTP) ROMs Spring 2018 – Lec. #6

2 可编程ROM（PROM） 总体结构与掩模ROM一样，但存储单元不同 写入时，要使用编程器 Spring 2018 – Lec. #6 EE141 2 可编程ROM（PROM） 总体结构与掩模ROM一样，但存储单元不同 写入时，要使用编程器 Spring 2018 – Lec. #6

3 可擦除的可编程ROM（EPROM） Erasable Programmable ROM EE141 3 可擦除的可编程ROM（EPROM） Erasable Programmable ROM 总体结构与掩模ROM一样，但存储单元不同 一、用紫外线擦除的PROM（UVEPROM） nonvolatile Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

二、电可擦除的可编程ROM（E2PROM） EE141 二、电可擦除的可编程ROM（E2PROM） Electrically Erasable PROM 总体结构与掩模ROM一样，但存储单元不同 Without a UV light source and a special PROM programmer unit Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

Electrically Erasable PROM Another advantage of the EEPROM over the EPROM is the ability to erase and rewrite individual bytes (eight-bit words) in the memory array electrically. This byte erasability makes it much easier to make changes in the data stored in an EEPROM. The early EEPROMs, such as Intel’s 2816, required appropriate support circuitry external to the memory chips, included the 21-V programming voltage (VPP). The newer devices, such as the Intel 2864, have integrated this support circuitry onto the same chip with the memory array, it requires only a single 5-V power pin. Spring 2018 – Lec. #6

Timing for the write operation. Spring 2018 – Lec. #6

三、快闪存储器（Flash Memory） EE141 The challenge for semiconductor engineers was to fabricate a nonvolatile memory with the EEPROM’s in-circuit electrical erasability, but with densities and costs much closer to those of EPROMs, while retaining the high-speed read access of both. 三、快闪存储器（Flash Memory） 为提高集成度，省去T2（选通管） 改用叠栅MOS管（类似SIMOS管） Spring 2018 – Lec. #6

Trade-offs for semiconductor nonvolatile memories show that complexity and cost increase as erase and programming flexibility increases. A typical flash memory has a write time of 10 ms per byte compared to 100 for the most advanced EPROM and 5 ms for EEPROM (which includes automatic byte erase time). Spring 2018 – Lec. #6

5.5.4 存储器容量的扩展 1. 位扩展方式 适用于每片RAM,ROM字数够用而位数不够时 接法：将各片的地址线、读写线、片选线并联即可 EE141 5.5.4 存储器容量的扩展 1. 位扩展方式 适用于每片RAM,ROM字数够用而位数不够时 接法：将各片的地址线、读写线、片选线并联即可 例：用八片1024 x 1位→ 1024 x 8位的RAM Spring 2018 – Lec. #6

2. 字扩展方式 适用于每片RAM,ROM位数够用而字数不够时 例：用四片256 x 8位→1024 x 8位 RAM 1024 x 8 EE141 2. 字扩展方式 适用于每片RAM,ROM位数够用而字数不够时 例：用四片256 x 8位→1024 x 8位 RAM 1024 x 8 RAM Spring 2018 – Lec. #6

EE141 1 Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

EE141 1 Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

5.5.5 用存储器实现组合逻辑函数 一、基本原理 从ROM的数据表可见： 若以地址线为输入变量，则数据线即为一组关于地址变量的逻辑函数 EE141 5.5.5 用存储器实现组合逻辑函数 一、基本原理 从ROM的数据表可见： 若以地址线为输入变量，则数据线即为一组关于地址变量的逻辑函数 地 址 数 据 A1 A0 D3 D2 D1 D0 1 A0~An-1 W0 W(2n-1) Spring 2018 – Lec. #6

5.5.5 用存储器实现组合逻辑函数 一、基本原理 从ROM的数据表可见： 若以地址线为输入变量，则数据线即为一组关于地址变量的逻辑函数 EE141 5.5.5 用存储器实现组合逻辑函数 一、基本原理 从ROM的数据表可见： 若以地址线为输入变量，则数据线即为一组关于地址变量的逻辑函数 地 址 数 据 A1 A0 D3 D2 D1 D0 1 Spring 2018 – Lec. #6

EE141 地 址 数 据 A1 A0 D3 D2 D1 D0 1 Spring 2018 – Lec. #6

EE141 二、举例 Spring 2018 – Lec. #6

EE141 Spring 2018 – Lec. #6

SPECIAL MEMORY FUNCTIONS Cache Memory First-In, First-Out Memory (FIFO) Circular Buffers Spring 2018 – Lec. #6

实例：PC to Memory (a) CPU address bus driving ROM or static-RAM memory; (b) CPU addresses driving a multiplexer that is used to multiplex the CPU address lines into the DRAM. Spring 2018 – Lec. #6

实例：Function Generator Spring 2018 – Lec. #6

课后作业 查阅： 作业： 自学Verilog HDL语言 阅读： 国际电路公司NXP，onsemi，fairchild，TI等的 EE141 课后作业 查阅： 国际电路公司NXP，onsemi，fairchild，TI等的 触发器、同步计数器、异步计数器芯片的型号手册、电参数、速度…… 图书馆资源：电子器件天地, 软件 作业： 《见学在浙里》 自学Verilog HDL语言 阅读： 推荐英文版电子书，“Digital_Systems_Principles_and_Applications”，CHAPTER 5 详细、实用较强； ch6.1-6.3; Ch6.4-6.6 Spring 2018 – Lec. #6