- Cellular Phone Content 3C Technology and Life - Cellular Phone Content Professor : 許 恒 銘 Rm.705, Professor Department of Electrical Engineering NCHU

Cellular - Phone History 1946年，貝爾實驗室-蜂巢行動電話(cellular mobile phone)，簡稱為Cell-phone. 1973年，摩托羅拉-兩塊磚頭大的無線電話撥打,代表著手機時代即將來臨的第一通電話 . 3G: CDMA2000，WCDMA，TD-SCDMA，三種通訊協定，在頻寬利用和數據通信方面都有進一步發展 ,分別支援2 Mbps、 384 Kbps以及144 Kbps等不同的傳輸速度 2G: 適應數位通訊的需要--增加數據、傳真、簡訊等非語音的數位訊號傳輸--每秒9.6～ 14.4 Kbps，速度太慢 2.5G: GPRS-搭配聲音、圖片、影像的多媒體簡訊 -傳輸速率大約為100 Kbps左右 1G: 上市是於1985年上市，重達3公斤

3.5G Cellular-Phone 高速下載封包存取- high speed downlink packet access (HSDPA）頻寬利用和數據通信都有進一步發展 加入適應調變編碼（AMC）、 多輸入多輸出（MIMO）傳送接收技術、 混合自動重傳請求（HARQ）、 快速調變、快速小區選擇等技術。 手機世代 推出時間 資料傳輸速率 通訊協定與調變系統 1G 1973 無 NMT AMPS、TACS 2G 1992 9.6~14.4 Kbps PHS、WAP CDMA 2.5G 1995 約100 Kbps PHS GSM、CDMA 3G 2002 300 K~1 Mbps CDMA2000 WCDMA、 TD-SCDMA 3.5G 2007 8~10 Mbps HSDPA

蜂巢式行動電話通訊系統 蜂巢理論模型 基地台涵蓋範圍示意圖

Wireless communication Evolution Ref. 2002 IEDM RF Short Course

Transceiver Architecture RF Front End Base Band Multi-Chip Module Flash Power Amplifier More than one IC’s were implemented into wireless products.

Benefits of System-on-Chip RF Baseband Bus PA One Single Chip ☺ Size ☺ Cost (Package,Die,..) ☺ Power consumption ☺ Customer orientation Module ☺ Time to market

Near Field of Antenna

IC technologies – 0.25um, 0.18um, 0.13um, 90nm,65nm,45nm Cross-sections of MOS (metal-oxide-semiconductor) transistor Gate N+ Source Drain P-well Bulk VDD

Technology Scaling Rule Technology (mm) Scale 0.5 0.3536 0.35 0.2475 0.25 0.1768 0.18 0.1273 0.13 0.0919 0.09 0.0636 0.065 0.046 0.045 0.0318

Wafer size – 6’’, 8’’, 12’’

System IC Business Diagram System IC is driving the whole semiconductor industry !

Building Block of Memory ICs High Capacitance / Low Leakage Current. High Packing Density / Low Process Cost.

Building Block of Logic ICs Fast Switching. High Current Drivability.

Multilevel interconnect with interlevel planarization ! Interconnection Why Multilevel Interconnect ? To allow tighter packing of devices on a chip improve interconnect limited device packing To reduce chip size and/or increase functions of a chip To minimize unnecessarily long interconnect route speed up signal delay Multilevel interconnect with interlevel planarization !

Impact of Interconnect Delay Interconnect will be dominant in signal delay Cu/Low-k retards the trend ~2 generations

Technology Roadmap Scaling continues for better performances !

Conclusions Frequencies & data rates will be continuous to increase All device functions will be merged into one single chip. IC is a promising & competitive area for production innovation.