Chapter 9 8086/8088 Hardware Specifications Instructor：Dr. Yu Youling
Content Architecture Pin-Outs and Pin Functions Clock generator 8284 Bus buffering and Latching Bus Timing Minimum Mode versus Maximum Mode 2019/2/25
Typical Architecture 2019/2/25
The 8066/8088 microprocessors The 8086, announced in 1978, was the first 16-bit microprocessor introduced by the INTEL 8086 and 8088 are internally 16-bit CPU, However, externally the 8086 has a 16-bit data bus and the 8088 has an 8-bit data bus Both 8086 and 8088 have the ability to address up to 1M of memory and 64K of input/output ports 2019/2/25
Device Specifications Both are packaged in DIP (Dual In-Line Packages) 8086: 16-bit microprocessor with a 16-bit data bus 8088: 16-bit microprocessor with an 8-bit data bus Both are 5V parts (i.e. VDD is 5V) 32 8086: Draws a maximum supply current of 360mA 8088: Draws a maximum supply current of 340mA 80C86/80C88: CMOS version draws 10mA Input/output characteristics: Yields a 350mV noise immunity for logic 0 (Output max can be as high as 450mV while input max can be no higher than 800mV). This limits the loading on the outputs. 2019/2/25
The pin-outs 2019/2/25
8086 CPU 8086 8088 No D8-D15 IO/M SS0 Pin 2-8, pin 39 Pin 28 Pin 34 2019/2/25
Pin-out Definitions 2019/2/25
Pin-out Definitions 2019/2/25
Pin-out Definitions 2019/2/25
Pin-out Definitions 2019/2/25
Pin-out Definitions 2019/2/25
8284 Clock Generator 2019/2/25
System Clock CLK waveform (1/3 for high and 2/3 for low) PCLK and CLK 2019/2/25
8284 Clock Generator Clock generation Crystal is connected to X1 and X2. XTAL OSC generates square wave signal at crystal's frequency which feeds: An inverting buffer (output OSC) which is used to drive the EFI input of other 8284As. 2-to-1 MUX F/C selects XTAL or EFI external input. The MUX drives a divide-by-3 counter (15MHz to 5MHz). This drives: The READY flipflop (READY synchronization). A second divide-by-2 counter (2.5MHz clk for peripheral components). The RESET flipflop. CLK which drives the 8086 CLK input. 2019/2/25
8284 Clock Generator RESET Negative edge-triggered flipflop applies the RESET signal to the 8086 on the falling edge. The 8086 samples the RESET pin on the rising edge. Correct reset timing requires that the RESET input to the microprocessor becomes a logic 1 NO LATER than 4 clocks after power up and stay high for at least 50μs. 2019/2/25
Bus Buffering and Latching Step Demultiplexing the Buses Driving Ability Dataflow Direction Address Control Data Example Address/Data Fig 9-6 Fully Buffered Fig 9-8 2019/2/25
Bus Buffering and Latching 2019/2/25
Bus Buffering and Latching With Place and Route 2019/2/25
BUS Timing Timing in General Co-operations among three buses need timing Address Control Data Bus Cycles Four system clock periods (T-States, T1,T2,T3,T3) 5MHz 1.25MIPS 2019/2/25
Bus Timing 8086处理器时序 指令周期—执行一条指令所需的时间。不同指令的指令周期是不同的。有些指令周期可划分为一个个总线周期。 例:最短指令: 寄←寄, 只需要2个时钟周期. 最长指令: 16位乘、除,约需200个时钟周期. 总线周期—每当CPU与存储器或I/O端口交换一个字节(或字、双字)数据所需的时间称之为一个总线周期。每个基本总线周期包含4个T状态。 T状态—就是一个时钟周期,是CPU处理动作的最小单位。 2019/2/25
时钟频率与T状态时钟频率一个T状态时间 基本的总线周期有 5M 200ns(0.2μs) 50M 20ns(0.02μs) 存储器的读周期或写周期 I/O端口的读周期或写周期 中断响应周期 2019/2/25
Bus Timing 2019/2/25
Bus Timing 2019/2/25
Bus Timing 2019/2/25
模式配置 为适应尽可能广泛的情况，8086（8088）微处理器有两种工作模式——最小模式和最大模式： 最小模式用于只有单个微处理器的小系统，8086直接产生所需的所有总线控制信号（从而最小化所需的总线控制逻辑）； 最大模式用于中、大系统（通常包括不止一个处理器），8086将基本总线控制信号编码为3个状态位，用多下来的控制引脚提供支持多处理器配置所需的附加信息。 2019/2/25
MIN and MAX Mode 2019/2/25
MIN Mode 8086 interface (Fig 9-20) 2019/2/25
MIN Mode 2019/2/25
MIN Mode 2019/2/25
MIN Mode 2019/2/25
MIN Mode 2019/2/25
MIN Mode 2019/2/25
MIN Mode 2019/2/25
MAX Mode Status Signal 2019/2/25
8288 Bus Controller 2019/2/25
MAX Mode 8086 Interface 2019/2/25
MAX Mode 2019/2/25
Homework 6,12,20,28,31,32 2019/2/25