Digital Circuitry CMOS Gate 刘 鹏 浙江大学 信息与电子工程学系 liupeng@zju.edu.cn

MOS管结构和符号 MOS: Metal-Oxide-Semiconductor Field-Effect Transistor VGS(th)称为MOS管的开启电压 VGS=0漏极和源极之间相当于两个PN结背向地串联，所以D-S间不导通. iD=0

CMOS 反相器 VDD＞VGS(th)N+|VGS(th)P|， VGS(th)N--NMOS的开启电压 VGS(th)P--PMOS的开启电压 VGS(th)N=|VGS(th)P| 工作原理： 1、输入为低电平VIL = 0V时 VGS1＜VGS(th)N T1管截止； 衬底与漏源间的PN结始终处于反偏，NMOS管的衬底总是接到电路的最低电位，PMOS管的衬底总是接到电路的最高电位 |VGS2| ＞ |VGS(th)P| T2导通 PMOS 电路中电流近似为零（忽略T1的截止漏电流）,VDD主要降落在T1上，输出为高电平VOH≈VDD 漏极相连做输出端 NMOS 2、输入为高电平VIH = VDD时，T1通T2止，VDD主要降在T2上，输出为低电平VOL≈0V。 柵极相连做输入端 实现逻辑“非”功能

与非门逻辑功能的CMOS门电路  电路实现“与非”逻辑功能 两个并联的PMOS管T3、T4 止 止 止 二输入“与非”门电路结构如图 通 1 当A和B为高电平时: 每个输入端与一 个 NMOS管和一个PMOS管的栅极相连 输出低电平 通 1 止 当A和B有一个或一个以上为低电平时: 1 1 两个串联的NMOS T1、T2 通 通 电路输出高电平  电路实现“与非”逻辑功能

或非门逻辑功能的CMOS门电路  电路实现“或非”逻辑功能 两个串联的PMOS管T1、T3 1 VDD 二输入“或非”门电路结构如图 B A B Y VDD 1 二输入“或非”门电路结构如图 止 通 当A和B为低电平时: 输出高电平 通 当A和B有一个或一个以上为高电平时: 1 通 两个并联的NMOS T1、T2 电路输出低电平 止  电路实现“或非”逻辑功能 止

漏极开路门电路（OD门） 1.电路组成 3.原理 必须外接负载电阻RL ，才能实现： 4.应用 2.逻辑符号 A Y B VDD2 RL & CD40107 外接上拉负载电阻 必须外接负载电阻RL ，才能实现： 4.应用 2.逻辑符号 与OC门一样，可做“线与”、“电平变换”等作用。 漏极开路 & A B Y

CMOS三态门 Y VDD T1 T2 T'1 A 1 T'2 1.电路组成 3.原理： 4.三态门的应用 主要应用： 总线逻辑 双向传输 2.逻辑符号 A Y

Transistor-level Logic Circuits (INV) Vdd Inverter (NOT gate): Gnd what is the relationship between in and out? Vdd in out 0 volts Gnd 3 volts

Logical Values +3 +3 Logic 1 Logic 0 Input Voltage V Vout +5 Vin Threshold Logical 1 (true) : V > Vdd –V th Logical 0 (false) : V < Vth Noise margin? F in out T not( out, in)

Computing with Switches Compose switches into more complex (Boolean) functions: A B AND Z  A and B A OR Z  A or B B Two fundamental structures: series (AND) and parallel (OR)

Transistor-level Logic Circuits - NAND NAND gate Logic Function: out = 0 iff both a AND b = 1 therefore out = (ab)’ pFET network and nFET network are duals of one another. Inverter (NOT gate): nand (out, a, b) a b out 0 0 1 0 1 1 1 0 1 1 1 0 How about AND gate?

Transistor-level Logic Circuits Simple rule for wiring up MOSFETs: nFET is used only to pass logic zero. pFet is used only to pass logic one. For example, NAND gate: Note: This rule is sometimes violated by expert designers under special conditions.

Transistor-level Logic Circuits - NOR NOR gate Function: out = 0 iff both a OR b = 1 therefore out = (a+b)’ Again pFET network and nFET network are duals of one another. Other more complex functions are possible. Ex: out = (a+bc)’ NAND gate a b out 0 0 1 0 1 0 1 0 0 1 1 0 nor (out, a, b)

Transmission Gate Transmission gates are the way to build “switches” in CMOS. Both transistor types are needed: nFET to pass zeros. pFET to pass ones. The transmission gate is bi-directional (unlike logic gates and tri-state buffers). Functionally it is similar to the tri-state buffer, but does not connect to Vdd and GND, so must be combined with logic gates or buffers.

Transistor-level Logic Circuits Variations Tri-state Buffer Transistor circuit for inverting tri-state buffer: “high impedance” (output disconnected) Inverting buffer Inverted enable “transmission gate” Tri-state buffers are used when multiple circuits all connect to a common bus. Only one circuit at a time is allowed to drive the bus. All others “disconnect”.

Transistor-level Logic Circuits - MUX Multiplexor If s=1 then c=a else c=b Transistor Circuit for inverting multiplexor:

Unused Inputs CMOS inputs should be never be left disconnected. All CMOS inputs must be tied either to a fixed voltage level (0V or VDD) or to another input. This rule applies even to the inputs of extra unused logic gates on a chip. An unconnected CMOS input is susceptible to noise and static charges that could easily bias both the P-channel and the N-channel MOSFETs in the conductive state, resulting in increased power dissipation and possible overheating.