外界影响 光注入 电注入

光敏电阻

电阻和电阻率

1.2 晶格振动 1.晶体原子离开其平衡位置的热振动 2.声子概念 3.电子和声子相互作用

1.3 Carrier Transport Phenomena mobility resistivity Basic Equation for Semiconductor-Device Operation Recombination processes

—mobility Vd=E -迁移率，表示单位场强下电子的平均漂移速度（cm2/V·s) I=-nqVd1 s J=- nqVd =-nq E Si: n=1350 cm2/V·s, p=500cm2/V·s

—mobility Ge, Si: 声学波散射（晶格振动）和电离杂质散射 声学波散射： 电离杂质散射： 总迁移率：

Scatter

—mobility III-V族：除共价键外，还有离子键成分，长纵光学波有重要的散射作用

—resistivity 1. J=E=nqnE+pqpE 2.集成电路电阻器

Basic Equation for Semiconductor-Device Operation —Basic Equations: Maxwell Equations: 如 （ ） 其中

Current-density Equations: One-dimensional:

—Recombination processes npni2（注入、抽取） np=ni2 非平衡载流子 非平衡载流子的复合： （1）直接复合：电子在导带和价带之间的直接跃迁，引起电子和空穴的直接复合 （2）间接复合：电子和空穴通过禁带的能级(复合中心）进行复合

—Recombination processes 直接复合

—Recombination processes 间接复合的四个过程 甲-俘获电子；乙-发射电子； 丙-俘获空穴；丁-发射空穴。 (b)过程后 （a)过程前

—Recombination processes recombination rate U(cm-3/s,单位时间、单位体积复合掉的电子-空穴对数): lifetime （小注入）

Continuity Equations: 三维：  由于电流，单位时间单位体积积累的空穴数： 三维：  where G – electron and hole generation rate, caused by external influence such as optical excitation or impact ionization. (小注入）

Semiconductor Fabrication SiGe HBT technology for circuit application

SiGe HBT The SiGe HBTs used were fabricated by IBM, and are typical of first-generation SiGe technology. A schematic cross-section is shown in Figure. The SiGe HBT has a planar, self-aligned structure with a conventional poly emitter contact, silicided extrinsic base, and deep- and shallow-trench isolation. The SiGe base was grown using UHV/CVD. The p-type substrate and the n-p-n layers of the intrinsic transistor form a n-p-n-p multi-layer structure,the p-type substrate is usually biased at the lowest potential ( 5.2 V here) for isolation.

MOSFET

MOSFET MOSFET circuit technology has dramatically changed over the last three decades. Starting with a ten-micron pMOS process with an aluminum gate and a single metallization layer around 1970, the technology has evolved into a tenth-micron self-aligned-gate CMOS process with up to five metallization levels. The transition from dopant diffusion to ion implantation, from thermal oxidation to oxide deposition, from a metal gate to a poly-silicon gate, from wet chemical etching to dry etching and more recently from aluminum (with 2% copper) wiring to copper wiring has provided vastly superior analog and digital CMOS circuits.

Figure:Cross-sectional view of a self-aligned poly-silicon gate transistor with LOCOS isolation

0.25m CMOS工艺 工艺1 工艺2

Technology 晶体生长与外延 —从熔体中生长单晶：直拉法(Si)和布里奇曼法(GaAs) 原材料：石英砂 SiC(固体)+SiO2(固体)Si(固体)+SiO(气体)+CO(气体) 冶金级硅 电子级硅（ppb量级） 硅片成形:前处理切片双面研磨抛光

光刻—图形曝光与刻蚀 —0.1m以内仍采用光学光刻技术 —短波长的射线：1nm波长软X射线、13nm波长极紫外线、电子束

  Transfer of a pattern to a photosensitive material

a) Pattern definition in positive resist, b) Pattern definition in negative resist

a) Pattern transfer from patterned photoresist to underlying layer by etching, b) Pattern transfer from patterned photoresist to overlying layer by lift-off.

各种光刻技术的优势及面临的技术挑战 157nm光学光刻技术 下一代光刻（NGL）技术 EUVL（极紫外光刻） XRL（X射线光刻）   157nm光学光刻技术 下一代光刻（NGL）技术 EUVL（极紫外光刻） XRL（X射线光刻） SCALPEL（限散射角电子束光刻） 基本原理 157nmF2激光投影光学光刻 4倍缩小扫描投影，约80层Mo-Si结构多层膜，激光等离子体光源，波长范围1113nm 1倍X射线接近式投影光刻，1X掩膜 4倍缩小电子束投影，钨（W）散射掩膜 前景 分辨率：80nm 应用领域：ULSI 分辨率:100nm延伸至30nm以下 分辨率:100nm延伸至40nm 应用领域：ULSI、GaAs IC、纳米加工、MEMS 100nm延伸至50nm 应用领域：ULSI、MEMS 重大课题 掩膜，薄膜，光刻胶，透镜成本，环境 无缺陷反射式掩膜、沾污控制；光学问题包括多层膜、光源（功率、寿命），设备成本占用率，真空环境 1X掩膜 空间电荷效应、 硅片表面热效应      

Homework 2 1.A p+-n junction is formed in an n type substrate with ND=1015cm-3. If the junction contains 1015cm-3 generation-recombination centers located 0.02eV above the intrinsic Fermi level of silicon with n=p=10-15cm2( Vth107cm/s), calculate the generation and recombination current at –0.5V.

2.Find the depletion-layer width and the maximum field at thermal equilibration for the p+-n1-n2 structure.